IDT EB8T5A Eval Board, Manual

Page: 46 / 48

LABEL:
1-2 : HOT-PLUG
PCIE X4 (1)
PORT 2
PORT 3
LABEL:
2-3 : PC PWR
2-3 : PC PWR
1-2 : HOT-PLUG
PCIE X4 (1)
Thu Apr 24 10:22:18 2008 SHEET 15 OF 17
1.0 18-636-002
D. Huang
2008
T. Tran
SCH-00162
89EBPES8T5A
B
14
11
7
4
14
4
14
14
14
15
5 12 15 16
12
15
11
4
14
10
10
10
15
8 9
15
4
8 9
7
11
14
12
5 12 15 16
14
R196
B9
B8
B7
B6
B5
B4
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J9
R209
C106 C107 C118 C119
R199
W32
W31
W30
C120 C121 C122
C123
W35
W34
W33
R190
W7
B9
B8
B7
B6
B5
B4
B32
B31
B30
B3
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B2
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B1
A9
A8
A7
A6
A5
A4
A32
A31
A30
A3
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A2
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A1
J14
W6
R193
5%
5.1K
5.1K
S2_PETN0
S3_12V
S3_WAKEN
0% 0
108051-301AC
10UF
25V
10UF
25V
10UF
25V
10UF
25V
0%
0
10UF
25V
10UF
25V
10UF
25V
10UF
25V
5%
S3_REFCLKN
S3_PERP0
S3_REFCLKP
S3_PERN0
S3_PETP0
S3_PETN0
S3_RSTN
U_PERSTN
P2RSTN
S2_RSTN
S3_3V
S2_REFCLKN
S2_PERN0
S2_12V
S2_3V
S2_3VAUX
PORT 2 AND PORT 3
S3_RSTN
P3PRDETN
S2_RSTN
S2_REFCLKP
NA
DNP
P2PRDETN
S2_WAKEN
108051-301AC
S3_3VAUX
S2_PERP0
P3RSTN
U_PERSTN
S2_PETP0
TITLE
DRAWING NO.
AUTHOR CHECKED BY
COPYRIGHT (C) IDT
3
SIZE REV. FAB P/N
1
1
A A
B B
C C
D
D
2
2
4
4 5
6
6 7
7
8
3 8 5
6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
OUT
OUT
IN
IN
PCIE_CONN_x4_OPEN_SLOT
GND
REFCLK-
RSVD
GND
PERP1
GND
GND
PERN2
3.3VAUX
RSVD
GND
PETN1
PRSTN2#
GND
RSVD
GND
PETN3
GND
GND
PETP3
PETN2
PETP2
GND
PERN3
PERP3
GND
GND
PERP2
GND
PERN1
+3.3V
GND
+3.3V
+12V
+12V
JTAG3
JTAG4
JTAG5
PERST#
GND
PERP0
GND
PERN0
RSVD
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
JTAG1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
GND
GND
PRSTN1#
+12V
WAKE#
JTAG2
3_3V
OUT
3_3V
IN
IN
IN
3_3V
12_0V
IN
3_3VAUX
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
3_3V
12_0V
IN
3_3VAUX
OUT
3_3V
OUT
IN
IN
OUT
PCIE_CONN_x4_OPEN_SLOT
GND
REFCLK-
RSVD
GND
PERP1
GND
GND
PERN2
3.3VAUX
RSVD
GND
PETN1
PRSTN2#
GND
RSVD
GND
PETN3
GND
GND
PETP3
PETN2
PETP2
GND
PERN3
PERP3
GND
GND
PERP2
GND
PERN1
+3.3V
GND
+3.3V
+12V
+12V
JTAG3
JTAG4
JTAG5
PERST#
GND
PERP0
GND
PERN0
RSVD
+12V
RSVD
SMCLK
SMDAT
+3.3V
GND
JTAG1
PETP1
PRSTN2#
GND
GND
PETP0
PETN0
GND
GND
PRSTN1#
+12V
WAKE#
JTAG2
IN
IN
OUT
IN
IN
OUT