IDT CPS-1848, User Manual

Page: 183 / 450

CPS-1848 User Manual 183 June 2, 2014
Formal Status This document is confidential and is subject to an NDA.
Integrated Device Technology
8. JTAG and Boundary Scan
This chapter discusses the functionality of the JTAG TAP port interface and Configuration Register Access (CRA) capability.
The chapter consists of two sections that describe Configuration Register Access: one for Revision A/B devices, and the other
for Revision C. All other content is applicable to all revisions of the CPS-1848. For the full specifications, see the CPS-1848
Datasheet.
Topics discussed include the following:
•
Overview
• JTAG and AC Extest Compliance
• Test Instructions
• Device ID Register
• Initialization and Reset
• Configuration Register Access (Revision A/B)
• Configuration Register Access (Revision C)
• JTAG Clock Constraints
• Boundary Scan
8.1 Overview
The CPS-1848 supports all the mandatory instructions defined in the IEEE 1149.1 Specification. The TAP Controller allows
access to the device’s configuration registers. Boundary scan testing of the AC-coupled I/Os are performed in accordance with
IEEE 1149.6 (AC Extest).
8.2 JTAG and AC Extest Compliance
All DC pins are compliant with the IEEE 1149.1 specification. All AC-coupled pins fully comply with the IEEE 1149.6
specification. All 1149.1 and 1149.6 boundary scan cells are on the same chain. No additional control cells are provided for
independent selection of negative and / or positive terminals of the Tx or Rx pairs.