8. JTAG and Boundary Scan > Configuration Register Access (Revision C)
CPS-1848 User Manual
187
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
8.7
Configuration Register Access (Revision C)
In addition to the S-RIO and I
2
C ports, the TAP Controller provides another interface to access any of the CPS-1848’s
configuration registers. Through the use of the “Configuration Register Access” opcode, writes and reads can be made to any
register. The same JTAG command and status instruction is used for both writes and reads of the Configuration Register space
(see
).
The system reset sequence for the CPS-1848 must be completed before a JTAG Configuration
Register Access operation is started.
Table 73: JTAG Configuration Register Access Command and Status Instruction
Bits
Field Name
Size
Description
0
READY
1
This is part of the status of the previous JTAG register access command. The
READY bit for the previous command is shifted out on TDO as the next
command is shifted in.
0b0 = Previous command did not have time to finish
0b1 = Previous command did have time to finish
The agent that applies JTAG register access commands is required to wait a
minimum period of time after issuing a command to allow that command to
finish (see
). If this minimum delay requirement is violated and
command B is applied too soon after command A, command A may not have
enough time to finish when its status is shifted out. In this case, the READY bit
that is shifted out for command A would be 0 and command B would be
ignored by the CPS-1848.
The value shifted into the READY bit is ignored by the CPS-1848.
1
ERROR
1
This is part of the status of the previous JTAG register access command. The
ERROR bit for the previous command is shifted out on TDO as the next
command is shifted in.
0b0 = Previous command finished without an error
0b1 = Previous command finished with an error
An error indication on this bit signals that an error occurred on the internal
configuration access register infrastructure within the CPS-1848. The nature
of the error is not accessible through this interface. Possible error causes
include: invalid address, parity error, and timeout.
The value shifted into the ERROR bit is ignored by the CPS-1848.
33:2
DATA
32
This is the write data for the current command that is shifted in on TDI. The
data for the previous instruction is shifted out on TDO.
Note: The data shifted in is not meaningful for Read or NOP commands
because these commands do not require input data.
If the previous command was a Read, the data shifted out is the read data for
that Read. If the previous command was a Write, the data shifted out is the
write data for that Write. If the previous command was a NOP, the data shifted
out is meaningless.
