8. JTAG and Boundary Scan > JTAG Clock Constraints
CPS-1848 User Manual
191
June 2, 2014
Formal Status
This document is confidential and is subject to an NDA.
Integrated Device Technology
8.8
JTAG Clock Constraints
The JTAG clock (TCK) must have a minimum period of 100 ns, and the minimum edge-to-edge spacing must be 40 ns
(see
).
Figure 47: JTAG Clock Constraints
8.9
Boundary Scan
JTAG instructions are provided to make all the device inputs observable and all the outputs controllable.
All external I/Os support Boundary Scan testing as defined in IEEE 1149.1 and 1149.6. All input / output possibilities are tested
including support for leakage testing, and providing users easy debugging by isolating the CPS-1848 from other devices on a
PCB board.
Minimum 100 ns
Minimum 40 ns
Minimum 40 ns
TCK
