IDT 89EBPES48H12, Manual

Page: 24 / 80

IDT Installation of the EB64H16 Eval Board
EB64H16 Eval Board Manual 2 - 12 January 16, 2007
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I
2
C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
The PES64H16 contains two SMBus interfaces: a slave SMBus interface and a master SMBus inter-
face. The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all
software-visible registers. The Master SMBus interface provides connection to the external serial
EEPROMs used for initialization and the I/O expander used for hot-plug signals.
SMBus Slave Interface
On the EB64H16 board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.11.
.
A fixed slave SMBus address specified by the SSMBADDR[5,3:1] pins is used.
For a fixed address, the SMBus address of the PES64H16 slave interface is
0b1110111 by default and
is configurable using jumpers W146, W147, W148, and W149 as described in Tables 2.12 and 2.13.
Slave SMBus Interface Connector
J34
Pin Signal
1 N/C
2 SSMBCLK
3 GND
4 SSMBDATA
Table 2.11 Slave SMBus Interface Connector
Slave Interface Address Configuration
Address Bit Signal
1 SSMBUSADDR[1]
2 SSMBUSADDR[2]
3 SSMBUSADDR[3]
4 0
5 SSMBUSADDR[5]
6 1
7 1
Table 2.12 SMBus Slave Interface Address Configuration