IDT Installation of the EB64H16 Eval Board
EB64H16 Eval Board Manual
2 - 10
January 16, 2007
Notes
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.9 is sampled by the PES64H16
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S5 and S6 as defined in Table 2.10.
13
W138
[1-2] Software controlled reset through GPIO18
[2-3] Fundamental reset PERST# (default)
14
W143
[1-2] Software controlled reset through GPIO19
[2-3] Fundamental reset PERST# (default)
15
W144
[1-2] Software controlled reset through GPIO20
[2-3] Fundamental reset PERST# (default)
Signal
Description
CCLKDS
Common Clock Downstream.
The assertion of this pin indicates that a common clock is
being used between the downstream device and the downstream port.
Default: 0x1
CCLKUS
Common Clock Upstream.
The assertion of this pin indicates that a common clock is
being used between the downstream device and the downstream port.
Default: 0x1
MSMBSMODE
Master SMBus Slow Mode.
The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz.
Default: 0x0
P01MERGEN
Port 0 and 1 Merge:
When this pin is asserted (i.e. low), port 1 is merged with port 0 to
form a single x8 port.
Default: 0x0
P23MERGEN
Port 2 and 3 Merge:
When this pin is asserted (i.e. low), port 2 is merged with port 3 to
form a single x8 port.
Default: 0x1
P45MERGEN
Port 4 and 5 Merge:
When this pin is asserted (i.e. low), port 4 is merged with port 5 to
form a single x8 port.
Default: 0x1
P67MERGEN
Port 6 and 7 Merge:
When this pin is asserted (i.e. low), port 6 is merged with port 7 to
form a single x8 port.
Default: 0x1
P89MERGEN
Port 8 and 9 Merge:
When this pin is asserted (i.e. low), port 8 is merged with port 9 to
form a single x8 port.
Default: 0x1
P1011MERGEN
Port 10 and 11 Merge:
When this pin is asserted (i.e. low), port 10 is merged with port 11
to form a single x8 port.
Default: 0x1
P1213MERGEN
Port 12 and 13 Merge:
When this pin is asserted (i.e. low), port 12 is merged with port 13
to form a single x8 port.
Default: 0x1
P1415MERGEN
Port 14 and 15 Merge:
When this pin is asserted (i.e. low), port 14 is merged with port 15
to form a single x8 port.
Default: 0x1
RSTHALT
Reset Halt.
When this signal is asserted during a PCI Express fundamental reset, the
PES64H16 executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.
Default: 0x0
Table 2.9 Boot Configuration Vector Signals (Part 1 of 2)
Port # Jumper
Selection
Table 2.8 Downstream Reset Selection (Part 2 of 2)
Summary of Contents for 89EBPES48H12
Page 4: ...IDT Table of Contents EB64H16 Eval Board Manual ii January 16 2007 Notes...
Page 6: ...IDT Table of Contents EB64H16 Eval Board Manual iv January 16 2007 Notes...
Page 8: ...IDT List of Figures EB64H16 Eval Board Manual vi January 16 2007 Notes...
Page 38: ...IDT Installation of the EB64H16 Eval Board EB64H16 Eval Board Manual 2 26 January 16 2007...
Page 40: ...IDT Software for the EB64H16 Eval Board EB64H16 Eval Board Manual 3 2 January 16 2007 Notes...
Page 41: ...Notes EB64H16 Eval Board Manual 4 1 January 16 2007 Chapter 4 Schematics Schematics...
