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VDDPEHA

VDDPEA

VDDPETA

VDDCORE

VDDIO

Fri Jun 15 14:48:05 2007

SHEET 13 OF 13

1.0

18-634-000

B.OH

2007

K. LEUNG

STGSCH-00114

89EBPES16T4G2

B

6

5

4

3

2

1

M1

C70

C75

C80

C85

C90

C100

C117

C122

C69

C74

C68

C73

C79

C78

C84

C89

C94

C99

C104

C108

C112

C116

C121

C126

C83

C88

C93

C98

C103

C107

C111

C115

C120

C125

C67

C72

C66

C71

C76

C77

C82

C87

C92

C97

C102

C106

C110

C114

C119

C124

C81

C86

C91

C96

C101

C105

C109

C113

C118

C123

C127

C132

C137

C147

C142

C157

C152

C160

C163

C166

C169

C172

C174

C176

C131

C136

C141

C146

C151

C156

C130

C135

C140

C150

C145

C155

C129

C134

C139

C149

C144

C154

C159

C162

C165

C168

C128

C133

C138

C143

C148

C153

C158

C161

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C167

C171

C170

C173

C175

C177

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C180

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C187

C188

C189

C95

H2

A12

J2

A11 M22 L22

L1 M1 W2 V2 V3 W3

A22

L2

B22 G22 W22

AB22

M21 P21 R21 U21 V21

AB21

AA2

L20 N20 P20 B19 F19 J19 M19 P19 U19

AB19

AB2

B18 B17 D17 W17 B15 B14 C14 D14 W14 C13

A1

B12 D12 Y12 C11 W11

AA11

Y10

D9

W9

Y9

D1

AA9

AA8

D6

W6

AA6

AA5

F4

J4

L4

P4

AA1

U4

AA4

J3

K3

M3

AA3

AB3

A2

E2

F2

AB1

W13 D10 W8 D7 D4 H4 N4 R3

D19 G19 K19 R19 W19 W16 D15

W4

AA10

B9

AA7

Y6
F3
L3
G2

J21

K2

N21
T21
M20
U20
C17
B16

AA14

B13
C12
Y11

P2

W10

D8
W7
D5
G4
K4
M4

E19

R4

H19
L19
N19
T19
W18
D16
W15
D13
W12
D11

V4

AB20
A19
Y15
C8
A3
Y3
D2
R2

C22
W21
H20

Y2

AB7 W5 A4 E4 AB4 G1 K1

D22 K22 N22

N1

T22 V19 D18 A16 AB16 A13 AB13 A10 AB10 A7

T1

U1

16V

0.1UF

0.1UF

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0.1UF

47UF

10V

47UF

10V

1UF

16V

0.1UF

0.1UF

16V

1UF

10V

47UF

10V

47UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

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0.1UF

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0.1UF

0.1UF

0.1UF

1UF

10V

47UF

16V

1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

10V

47UF

0.1UF

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0.1UF

0.1UF

0.1UF

0.1UF

47UF

10V

0.1UF

47UF

10V

0.1UF

0.1UF

0.1UF

0.1UF

89HPES16T4G2 - POWER

0.1UF

TITLE

DRAWING NO.

AUTHOR

CHECKED BY

COPYRIGHT (C) IDT

3

SIZE

REV.

FAB P/N

1

1

A

A

B

B

C

C

D

D

2

2

4

4

5

6

6

7

7

8

3

8

5

6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138

CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.

+1.0V_VDDA

+2.5V_VDDHA

+1.0V_VDDTA

+1.0V_CORE

STIFF_6P

3_3VIO

3_3V

+1.0V_VDDA

+2.5V_VDDHA

+1.0V_CORE

+1.0V_VDDTA

89HPES16T4G2 (4 of 4)

VSS80

VSS79

VSS78

VSS77

VSS76

VSS75

VSS74

VSS73

VSS72

VSS71

VSS70

VSS69

VDDCORE22

VDDCORE21

VDDCORE19

VDDCORE20

VSS44

VSS17

VSS16

VSS15

VSS41

VSS42

VSS48

VSS49

VDDCORE18

VDDCORE17

VDDCORE16

VDDCORE15

VDDCORE14

VDDCORE13

VDDCORE12

VDDCORE11

VDDCORE10

VDDCORE9

VDDCORE8

VDDCORE7

VDDCORE6

VDDCORE5

VDDCORE4

VDDCORE3

VDDCORE2

VDDCORE1

VDDPETA7

VSS68

VSS67

VSS66

VSS65

VSS64

VSS63

VSS62

VSS61

VSS60

VSS59

VSS58

VSS57

VSS56

VSS55

VSS54

VSS53

VSS52

VSS51

VSS50

VSS47

VSS46

VSS45

VSS43

VSS40

VSS39

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VSS35

VSS34

VSS33

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS18

VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

VSS8

VSS7

VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VDDPEHA20

VDDPEHA19

VDDPEHA18

VDDPEHA17

VDDPEHA16

VDDPEHA15

VDDPEHA14

VDDPEHA13

VDDPEHA12

VDDPEHA10

VDDPEHA9

VDDPEHA8

VDDPEHA7

VDDPEHA6

VDDPEHA5

VDDPEHA4

VDDPEHA3

VDDPEHA2

VDDPEHA1

VDDPEA20

VDDPEA19

VDDPEA18

VDDPEA17

VDDPEA16

VDDPEA13

VDDPEA12

VDDPEA11

VDDPEA10

VDDPEA9

VDDPEA8

VDDPEA7

VDDPEA6

VDDPEA5

VDDPEA4

VDDPEA3

VDDPEA2

VDDPEA1

VDDIO12

VDDIO11

VDDIO10

VDDIO9

VDDIO8

VDDIO7

VDDIO6

VDDIO5

VDDIO4

VDDIO3

VDDIO2

VDDIO1

VDDPETA2

VDDPETA1

VDDPETA3

VDDPETA5

VDDPETA4

VDDPETA8

VDDPETA6

VDDPETA10

VDDPETA9

VDDPETA12

VDDPETA13

VDDPETA11

VDDPETA14

VDDPETA15

VDDPETA16

VDDPEA15

VDDPEA14

VDDPEHA11

3_3VIO

Summary of Contents for 89EBPES16T4G2

Page 1: ...lver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2007 Integrated Device Technology Inc IDT 89EBPES16T4G2 Evaluation Board Manual E...

Page 2: ...ure Analysis be performed LIFE SUPPORT POLICY Integrated Device Technology s products are not authorized for use as critical components in life support devices or systems unless a specific written agr...

Page 3: ...Express Analog Power Voltage Converter 2 3 PCI Express Transmitter Analog Power Voltage Converter 2 3 Core Logic Voltage Converter 2 3 3 3V I O Voltage Regulator 2 3 Power up Sequence 2 3 Required Jum...

Page 4: ...IDT Table of Contents EB16T4G2 Eval Board Manual ii October 3 2007 Notes...

Page 5: ...6 Downstream Reset Selection 2 4 Table 2 7 Boot Configuration Vector Signals 2 4 Table 2 8 Boot Configuration Vector Switches S7 S8 ON 0 OFF 1 2 5 Table 2 9 Slave SMBus Interface Connector 2 6 Table...

Page 6: ...IDT List of Tables EB16T4G2 Eval Board Manual iv October 3 2007 Notes...

Page 7: ...Notes EB16T4G2 Eval Board Manual v October 3 2007 List of Figures Figure 1 1 Function Block Diagram of the EB16T4G2 Eval Board 1 1...

Page 8: ...IDT List of Figures EB16T4G2 Eval Board Manual vi October 3 2007 Notes...

Page 9: ...ts The EB16T4G2 eval board is designed to function as an add on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appropriate root complex microprocessor s and three downstr...

Page 10: ...ed to the Serial EEPROMs through I O expander Attention button for each downstream port to initiate a hot swap event on each port Four pin connector for optional external power supply Push button for...

Page 11: ...4G2 has three PCI Express downstream ports accessible through three x16 connectors All three ports are capable of negotiating a x1 x2 or x4 link width All endpoint cards connected to the PES16T4G2 mus...

Page 12: ...n support an external source is required to supply this extra power via an auxiliary 4 pin power connector on the board Header W1 W2 and W3 see Table 2 14 are used to select proper power source for th...

Page 13: ...power supply ramp up VDDCORE must remain at least 1 0V below VDDIO at all times There are no other power up sequence requirements for the various operating supply voltages Required Jumpers To deliver...

Page 14: ...eset while PERSTN is active The boot configuration vector defines the essential parameters for switch operation and is set using DIP switches S7 and S8 as defined in Table 2 8 Port Jumper Selection 2...

Page 15: ...itch operating mode Default 0x0 0x0 Normal switch mode 0x1 Normal switch mode with Serial EEPROM based initialization 0x2 through 0x7 Reserved REFCLKM PCI Express Reference Clock Mode Select This sign...

Page 16: ...signals SMBus Slave Interface On the PES16T4G2 board the slave SMBus interface is accessible through the PCI Express edge connector as well as a 4 pin header as described in Table 2 9 Note The SMBus...

Page 17: ...provides a JTAG connector J5 for access to the PES16T4G2 JTAG interface The connector is a 2 54 x 2 54 mm pitch male 10 pin connector Refer to Table 2 15 for the JTAG Connector J5 pin out Attention Bu...

Page 18: ...om Upstream port Default 1 2 Port 2 12V source from hot plug controller W9 Header 2 3 Shunted 2 3 Port 4 12V source from Upstream port Default 1 2 Port 4 12V source from hot plug controller W12 Header...

Page 19: ...Port 6 Power Indicator DS19 Yellow Port 2 Attention Indicator DS7 Yellow Port 4 Attention Indicator DS13 Yellow Port 6 Attention Indicator DS18 Green Port2 Activity Indicator DS6 Green Port4 Activity...

Page 20: ...REFCLK REFCLK Reference clock 14 PETp0 Transmitter differential REFCLK differential pair 15 PETn0 pair Lane 0 GND Ground 16 GND Ground PERp0 Receiver differential 17 PRSNT2 Hot Plug presence detect PE...

Page 21: ...nd 50 PETp8 Transmitter differential RSVD Reserved 51 PETn8 pair Lane 8 GND Ground 52 GND Ground PERp8 Receiver differential 53 GND Ground PERn8 pair Lane 8 54 PETp9 Transmitter differential GND Groun...

Page 22: ...ogether This allows the board to be installed in a x1 or a x4 slot via a slot reducer 71 PETn13 pair Lane 13 GND Ground 72 GND Ground PERp13 Receiver differential 73 GND Ground PERn13 pair Lane 13 74...

Page 23: ...IDT Installation of the EB16T4G2 Eval Board EB16T4G2 Eval Board Manual 2 13 October 3 2007 EB16T4G2 Board Figure...

Page 24: ...IDT Installation of the EB16T4G2 Eval Board EB16T4G2 Eval Board Manual 2 14 October 3 2007 Notes...

Page 25: ...te a configuration file into an EEPROM programmable data structure This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES16T4G2 and then to populate...

Page 26: ...IDT Software for the EB16T4G2 Eval Board EB16T4G2 Eval Board Manual 3 2 October 3 2007 Notes...

Page 27: ...Notes EB16T4G2 Eval Board Manual 4 1 October 3 2007 Chapter 4 Schematics Schematics...

Page 28: ...R 1 TITLE PAGE SHEET DESCRIPTION Tue Oct 02 16 57 16 2007 SHEET 1 OF 13 K LEUNG 2007 STGSCH 00114 B OH 1 0 18 634 000 89EBPES16T4G2 B STGC 0114R01 1 0 INITIAL RELEASE 2007 10 02 K LEUNG 6 A TITLE CHEC...

Page 29: ...1UF YEL YEL 330 PERST_N 330 GRN RED 5 47UF 12V_DS 5 10K 10K 5 5 10K RED 0 0 10V 220UF 47UF 10V 1 21K 1 22UF 25V 22UF 25V 25V 10UF 25V 10UF 22UF 25V 10V WHT WHT WHT WHT 5 12 11 10 9 2 8 2 8 TITLE DRAWI...

Page 30: ...10UF 10UF 10UF 10UF 10UF 400MA 400MA 400MA 1UF 120OHM 120OHM 120OHM 16V 1UF 0 0 015UF 0 16V 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 1UF 0 1UF 400MA 120OHM 120OHM 400MA 16V 120OHM 1 16V 1UF 0 1UF 1UF...

Page 31: ...3 2 1 6 9 7 13 11 15 14 10 U4 R14 R19 9 8 10 7 11 6 12 5 13 4 14 3 15 2 16 1 S2 4 3 1 2 Y1 C16 8 12 9 10 11 8 12 9 10 11 6 5 9 6 5 11 6 5 10 12 12 10 10 8 8 M_SSMBCLK M_SSMBDATA P2_PWRGDN P6_PWRGDN P...

Page 32: ...M_SDA P0_LINKUPN P4_APN 0 0 0 P4_PDN IO EXP WAKE ATTN BUTTONS M_IOINTN0 0 YEL P2_MRLN YEL P2_ILOCKP YEL YEL P6_MRLN P6_ILOCKP P4_PFN P4_PEP P4_PIN P4_AIN P4_APN P6_WAKE_N YEL P4_ILOCKP YEL P4_MRLN 10...

Page 33: ...LUG CONTROLLERS P6_12VSENSE P6_12VGATE P6_12VOUT P4_12VGATE P6_3VSENSE P6_3VGATE P6_3VOUT P6_VAUX P2_VAUX P4_12VSENSE P4_VAUX P2_3VSENSE P24_INTN P6_INTN P4_PEP P2_PEP 10K 10K 10K 10K 10K 10K 110K 0 1...

Page 34: ...12V P6_3_3V 12V_DS P2_PCIE_3_3AUX P2_12V P2_3_3V P4_PCIE_3_3AUX P4_12V P4_3_3V P4_3VSENSE P4_3VGATE P6_12VGATE P6_12VOUT P6_3VOUT P2_3VOUT P2_3VGATE P2_3VSENSE P2_12VOUT P2_12VGATE P2_12VSENSE P4_3VOU...

Page 35: ..._PETN3 PORT 0 UPSTREAM EDGE CONN P0_REFCLKP P0_PERP0 PERST_N P0_ACTIVEN P0_PERP1 P0_PERP3 P0_PERP2 1K 1K P0_PERN0 M_SSMBCLK P0_LINKUPN DNP 5 330 10UF 25V 10UF 25V 10UF 25V GRN GRN 330 5 M_SSMBDATA TIT...

Page 36: ...OR 0 0 GRN GRN 5 330 330 5 GRN 5 330 5 330 GRN YEL 5 5 1K 10UF 10UF 25V 10UF 25V 10UF 25V DNP DNP P2_12V P2_3_3V P2_12V P2_3_3V 5 330 GRN M_P2_PERST_N 330 M_SSMBDATA M_PERSTN P2_PDN 5 P2_AIN P2_PIN P2...

Page 37: ...0UF 25V 10UF 25V P4_12V P4_3_3V P4_PCIE_3_3AUX P4_3_3V DNP DNP GRN 330 5 P4_ACTIVEN P4_AIN GRN P4_PERST_N M_P4_PERST_N PORT 4 CONNECTOR P4_PWRGDN P4_PIN P4_LINKUPN 330 M_PERSTN P4_PDN 0 0 M_SSMBDATA M...

Page 38: ...N P6_LINKUPN P6_ACTIVEN M_SSMBDATA M_PERSTN P6_PERST_N M_P6_PERST_N P6_PDN P6_PIN P6_AIN P6_PETN3 P6_PETP3 P6_PETN2 P6_PETN0 P6_PETP1 P6_PETN1 P6_PETP2 P6_WAKE_N P6_PERP3 P6_PERN2 P6_PERN0 P6_PERP0 P6...

Page 39: ...5 52 298 000 P0_PETP1 P0_PETN0 P0_PETP0 M_P6_PERST_N M_SDA M_SCL JTAG_RST_N M_P2_PERST_N M_P4_PERST_N M_IOINTN0 M_IOINTN2 YEL YEL M_GPEN 12 5 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 5 11 10 9 4 8...

Page 40: ...F 0 1UF 10V 47UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1...

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