ICS PCI-WDT 500, Product Manual

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Manual Number: 00650-144-1 Page 6
PCI-WDT 500/501 Manual
The duration of the watchdog reset output (WDRST) and (Not WDRST) can be programmed at
counter 2. There are two clock rates available for the counter and you can select the rate that best
suits your needs. The default clock rate is half the PCI bus clock speed, 16.67 MHz. You can select
a lower rate (2.08333 MHz) by a write to base C. That selection will be held until reset by
the computer.
The watchdog card can generate an interrupt request one counter 0 period-width before the reset
timeout. For example, if a reset period of 60 seconds is used with a 5 millisecond delay stored in
counter 0 (the result of a maximum value delay), an interrupt would occur at 59.995 seconds. This
gives the interrupt handler software 5 milliseconds to refresh the watchdog before a reset action
occurs. This should allow your software to take corrective actions if the system software continued
to run but the software that should have reset the watchdog had failed.
The interrupt request (IRQ) output is tri-stated at a high-impedance when it is not sending an
interrupt request (1 msec). Thus, that IRQ number can be shared with other I/O cards that have
shareable ability. The system assigns the IRQ level when the card is installed.
There are several outputs from the watchdog circuit as listed below (See Section 6 for pinout.)
a. Double-pole double-throw, Form C, relay contacts on the rear panel I/O connector
b. An opto-isolated reset output on the rear panel I/O connector
c. An opto-isolated complement of the reset output on the rear panel I/O connector
d. A buffered TTL CTRGATE (counter enabled) output on the rear panel I/O connector
e. TTL Reset signal (active high) on internal terminal block
f. The complement of that Reset signal on internal terminal block
g. A watchdog 130.208KHz “heartbeat” on the rear panel I/O connector
h. Unfused 5VDC output at the rear panel I/O connector
i. Fan Drive Power return on internal terminal block
j. Fan Drive Power out on internal terminal block
k. “System Shutdown” (on PCI-WDT501) can initiate computer shutdown if the fan stops
As noted in items b and c above, opto-coupler outputs (one ON when the other is OFF) are pro-
vided for use where relay contact bounce could be a problem. Further, as noted in e. above, a
buffered discrete output is also provided. This output goes high to signal a watchdog reset condi-
tion. Finally, a 130.208 KHz, TTL-level, 50% duty cycle signal is provided at I/O connector pin 13
when the watchdog circuit is enabled and no reset is in progress. Otherwise, this output is in a low
state.