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Manual Number: 00650-144-1

Page 6

PCI-WDT 500/501 Manual

The duration of the watchdog reset output (WDRST) and (Not WDRST) can be programmed at

counter 2.  There are two clock rates available for the counter and you can select the rate that best

suits your needs.  The default clock rate is half the PCI bus clock speed, 16.67 MHz.  You can select

a lower rate (2.08333 MHz) by a write to base C.  That selection will be held until reset by

the computer.

The watchdog card can generate an interrupt request one counter 0 period-width before the reset

timeout. For example, if a reset period of 60 seconds is used with a 5 millisecond delay stored in

counter 0 (the result of a maximum value delay), an interrupt would occur at 59.995 seconds. This

gives the interrupt handler software 5 milliseconds to refresh the watchdog before a reset action

occurs. This should allow your software to take corrective actions if the system software continued

to run but the software that should have reset the watchdog had failed.

The interrupt request (IRQ) output is tri-stated at a high-impedance when it is not sending an

interrupt request (1 msec). Thus, that IRQ number can be shared with other I/O cards that have

shareable ability.  The system assigns the IRQ level when the card is installed.

There are several outputs from the watchdog circuit as listed below (See Section 6 for pinout.)

a. Double-pole double-throw, Form C, relay contacts on the rear panel I/O connector
b. An opto-isolated reset output on the rear panel I/O connector
c. An opto-isolated complement of  the reset output on the rear panel I/O connector
d. A buffered TTL CTRGATE (counter enabled) output on the rear panel I/O connector
e. TTL Reset signal (active high) on internal terminal block
f. The complement of that Reset signal on internal terminal block
g. A watchdog 130.208KHz “heartbeat” on the rear panel I/O connector
h. Unfused 5VDC output at the rear panel I/O connector
i. Fan Drive Power return on internal terminal block
j. Fan Drive Power out on internal terminal block
k. “System Shutdown” (on PCI-WDT501) can initiate computer shutdown if the fan stops

As noted in items 

b

 and 

above,  opto-coupler outputs (one ON when the other is OFF) are pro-

vided for use where relay contact bounce could be a problem. Further, as noted in e. above, a

buffered discrete output is also provided. This output goes high to signal a watchdog reset condi-

tion.  Finally, a 130.208 KHz, TTL-level, 50% duty cycle signal is provided at I/O connector pin 13

when the watchdog circuit is enabled and no reset is in progress. Otherwise, this output is in a low

state.

Summary of Contents for PCI-WDT 500

Page 1: ...Model PCI WDT 500 501 Product Manual MANUAL NUMBER 00650 144 1B...

Page 2: ...ual in our online Support Library Thank you The information in this document is provided for reference only ICS Advent does not assume any liability arising from the application or use of the informat...

Page 3: ...Page iv This page intentionally left blank...

Page 4: ...ts which are not in an as new and re saleable condition are not eligible for credit return and will be returned to the customer Limited Warranty Effective April 1 1998 all products carry a 2 year limi...

Page 5: ...made by various manufacturers in performing warranty repairs and building replacement products If ICS Advent repairs or replaces a product its warranty term is not extended ICSAdvent will normally re...

Page 6: ...Cautions and Warnings are accented with triangular symbols The exclamation symbol is used in all cautions and warnings to help alert you to the important instructions The lightning flash symbol is us...

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Page 8: ...emperature Measurement 7 Change of State 7 Fan Speed 7 Buzzer 7 Opto Isolated Outputs 7 Status Register 8 Utility Software 8 Chapter 3 Option Selection 11 Relay Enable Disable 11 Screw Terminals 11 LE...

Page 9: ...gramming 28 Reading and Loading The Counters 29 List of Figures Figure 1 Block Diagram 9 Figure 2 WDG50x Option Selection Map 12 List of Tables Table 1 Buzzer operation requires configuring Counter 2...

Page 10: ...installation process will create several directories on your hard disk If you accept the instal lation defaults the following structure will exist From the diskette titled PCI WDGCSM PCIWDGCSM Root o...

Page 11: ...uilder 1 0 See Section 5 of this manual for more information Four functions are provided unsigned int InPortB unsigned int BaseAddress unsigned int InPort unsigned int BaseAddress void OutPortB unsign...

Page 12: ...t You may need to remove a backplate first 5 Inspect for proper fit of the card and tighten screws Make sure that the card mounting bracket is properly screwed into place and that there is a positive...

Page 13: ...Connections Connections are made via a 25 pin connector on the card mounting bracket Also there is a six terminal terminal block Signal assignments are listed in Section 6 of this manual To ensure tha...

Page 14: ...the watchdog will continuously reset the computer The more frequently the watchdog is prompted and shorter watchdog time selected the less time a faulty computer has to cause dam age The method used...

Page 15: ...ave shareable ability The system assigns the IRQ level when the card is installed There are several outputs from the watchdog circuit as listed below See Section 6 for pinout a Double pole double thro...

Page 16: ...18 ISOIN0 Pins 19 and 20 ISOIN1 are opto isolated and reported in the Status Register The change of state also generates an IRQ interrupt request Fan Speed This function is usable only in computers wh...

Page 17: ...upply undervoltage Active low BD7 IRQ generated Active low Utility Software Utility software is provided on the diskette with the PCI WDT50x card This software includes a SETUP EXE an illustrated setu...

Page 18: ...Manual Number 00650 144 1 Page 9 1 R W H 6 K D G H G D U H D V D U H I H D W X U H V R I W K H 3 7 LJXUH ORFN LDJUDP 8 V H U P D V X S S O D Q G L Q V W D O O D W W K L V S R L Q W...

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Page 20: ...d if a jumper is placed between the two right hand posts the relay is energized during reset watchdog timeout If you desire to use the relay output then the jumper should be placed between the right h...

Page 21: ...erminals A connector for an external or onboard LED is provided at two solder pads labeled J2 The output is limited by a 470 ohm resistor in series with a 5V output This output is only active if the b...

Page 22: ...that has been assigned run the pro vided PCIFind EXE utility program Alternatively some operating systems Windows95 and WindowsNT 5 0 can be queried to deter mine which resources were assigned In the...

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Page 24: ...A e s a B 2 r e t n u o C d a e R 2 r e t n u o C o t e t i r W 3 s s e r d d A e s a B r e t s i g e R l o r t n o C d a e R r e t s i g e R l o r t n o C o t e t i r W 4 s s e r d d A e s a B r e t...

Page 25: ...Active low BD1 Temperature good Active high BD2 Isolated Input 0 status Same as input BD3 Isolated Input 1 status Same as input BD4 Fan good Active high BD5 Power Supply overvoltage Active low BD6 Po...

Page 26: ...m the counters In summary Disable Watchdog Read BASE 7 Program CTR0 for Mode 3 See Appendix A Program CTR1 for Mode 2 See Appendix A Load CTR0 1 with reset delay See Appendix A Enable Watchdog Write B...

Page 27: ...tine would prompt the watchdog under normal conditions and the ISR running in the background would only prompt the watchdog if the foreground routine failed to do so The ISR noting that the foreground...

Page 28: ...REQUIRED modes CtrMode 1 2 CtrMode 2 1 LoadCtr 0 1 1 is full load value long reset and high granular LoadCtr 1 10 END End set_counter VAR read_back BYTE loop WORD ch CHAR BEGIN clrscr writeln Pascal...

Page 29: ...oject similar to the sample provided or else modify your existing project file and include the GBL file File Add File Once this has been done VisualBASIC will be enhanced with the addition of the foll...

Page 30: ...signed numbers wherein data are stored in two s complement form All bit patterns must be converted to and from this two s complement form if meaningful display is required Otherwise values returned f...

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Page 32: ...e t a l o s I o t p O 8 d e l b a n E r e t n u o C 9 x a m A 1 d e s u f n U C D V 5 0 1 C D V 5 1 1 C D V 5 2 1 C D V 5 3 1 d e l b a n e G O D W e l i h w e v a W e r a u q S z H K 8 0 2 0 3 1 4 1...

Page 33: ...o L e v i t c A t u p t u O g o d h c t a W L T T l a n i m r e T d n 2 d n u o r G l a n i m r e T d r 3 h g i H e v i t c A t u p t u O g o d h c t a W L T T l a n i m r e T h t 4 r e w o P e v i r...

Page 34: ...Q and status register indication at 122 F and above 3 Temp Sensor 8 bit ADC LSB 0 7 F factory adjustable 4 Fan Speed IRQ and status register indication whenever tachometer output drops below 50pps cus...

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Page 36: ...dcall external Win32IRQ dll index 1 function DetectIRQ Boolean stdcall external Win32IRQ dll index 2 function SendEOI Boolean stdcall external Win32IRQ dll index 3 In C the library file Win32IRQ lib m...

Page 37: ...ogram needs to continue running while waithing for DetectIRQ a separate thread should be spawned from which to call DetectIRQ The return result is TRUE if an IRQ was successfully detected on the given...

Page 38: ...ternal Win32IRQ dll index 1 function DetectIRQ Boolean stdcall external Win32IRQ dll index 2 function SendEOI Boolean stdcall external Win32IRQ dll index 3 In C the library file Win32IRQ lib must firs...

Page 39: ...ogram needs to continue running while waithing for DetectIRQ a separate thread should be spawned from which to call DetectIRQ The return result is TRUE if an IRQ was successfully detected on the given...

Page 40: ...s high until a new count is loaded into the counter A trigger enables the counter to start decrementing This mode is commonly used for event counting with counter 0 Mode 1 Retriggerable One Shot The o...

Page 41: ...ments by two for the total loaded count then reloads and decre ments by two for the second part of the waveform Mode 4 Software Triggered Strobe This mode sets the output high and when the count is lo...

Page 42: ...R 0 W R 2 M 1 M 0 M D C B SC0 and SC1 These bits select the counter that the control byte is destined for 1 C S 0 C S n o i t c n u F 0 0 0 r e t n u o C m a r g o r P 0 1 1 r e t n u o C m a r g o r...

Page 43: ...W R 2 M 1 M 0 M D C B OUT Current state of counter output pin NC Null count This indicates when the last count loaded into the counter register has actually been loaded into the counter itself The ex...

Page 44: ...ESD Immunity EN61000 4 3 1995RadiatedRFFieldImmunity EN61000 4 4 1995EFTImmunityforACandI OLines EN 60950 1992 Safety of InformationTechnology Equipment Thetechnicaldocumentationrequiredtodemonstratet...

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