Epson CARD-GX Hardware Manual Download

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MF1286-02

SEIKO EPSON CORPORATION

CARD-PCI/GX

Hardware Manual

Summary of Contents for CARD-GX

Page 1: ...MF1286 02 SEIKO EPSON CORPORATION CARD PCI GX Hardware Manual ...

Page 2: ...h this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from anther government agency ...

Page 3: ...s Interface specifications Interface specifications Interface specifications 18 18 18 18 3 1 Pin configuration 18 3 1 1 280 pin connector pin configuration 19 3 1 2 20 pin connector pin configuration 19 3 2 Signal characteristics 21 3 3 Descriptions on signal functions 27 3 3 1 PCI bus 27 3 3 2 LIMITED ISA bus 28 3 3 3 LCD 30 3 3 4 CRT 31 3 3 5 Hard disk IDE 31 3 3 6 USB 31 3 3 7 Serial interfaces...

Page 4: ...ch is not turned ON OFF from the software 51 6 6 6 6 Electrical characteristics Electrical characteristics Electrical characteristics Electrical characteristics 52 52 52 52 6 1 Absolute maximum rating 52 6 2 Recommended operating condition 52 6 3 DC characteristics under recommended operating condition 53 6 3 1 PCI bus 53 6 3 2 LIMITED ISA bus 53 6 3 3 LCD 54 6 3 4 CRT 54 6 3 5 FDD 55 6 3 6 IDE 55...

Page 5: ...ection of 5V device to PCI bus 69 A 2 IO extension of LIMITED ISA bus 70 A 2 1 Address decoding 70 A 2 2 Pull up of SD SA 7 0 70 A 2 3 SA 15 0 latch 71 A 2 4 Number of ISA slots 71 A 2 5 Pull up resistance of IOCHRDY 71 A 2 6 SMEMR and SMEMW generation 72 A 2 7 MEMCS16 generation 72 A 3 Power supply design Power control circuit 73 A 3 1 Power not requiring ON OFF by software 73 A 3 2 Power requiri...

Page 6: ...ality display CRT1280 1024 256 color are all realized Especially this low power consumption capability is one of the most important aspects to realize fan less which is required in applications requiring high liability All these capabilities are provided within a compact size of 101 6 1 0 63 5 0 3 16 0 1 0 mm with 280 pin and 20 pin interface connectors Because SCE8720C can easily enable the core ...

Page 7: ...mpanion chip 97317 Super IO all built in As the main memory SCE8720Cxx has a 32MB or 64MB of synchronous D RAM and has utilized the unified memory method in which a part of the synchronous D RAM is used as the display memory Generally it is said that the unified memory method results in low performance However with SCE8720Cxx high performance is realized by compressing the data for display refresh...

Page 8: ...XGA 64K color STN cannot be used I O interface PCI 3 3V PCI Version 2 1 Compliance 33MHz PCI device 3 PCI master 2 LIMITEDISA No DMA or Master function provided As for AB0 15 multiplex output to DB Some signals have been deleted as well Parallel 1 port SPP ECP EPP rev1 9 1 7 supported Serial 2 port 16550 compatible Max 1 5Mbaud HDD IDE 1 device ANSI ATA_4 Compliant FDD 1 device 720 1 44MB 2mode 3 ...

Page 9: ...are measured when Windows 98 is running and desktop is displayed CPU_VRM power supply VCCCORE 5V Current consumption Typ 408mA Standby current Typ 17 2 mA System power VCC3V 3 3V Current consumption Typ 620 mA Standby current Typ 230 mA ISA bus power supply VCC5V 5V Current consumption Typ 17 1 mA Standby current Typ 11 5 mA 5V standby power VCCSTB 5V Power of 5V is always supplied regardless of t...

Page 10: ...1 power SW Power OFF Soft OFF Standby mode 1 3 BIOS SCE8720C has adopted AWARD BIOS manufactured by Phoenix It has the power management and plug and play functions With the BIOS setup menu many configuration parameters can be set The Video BIOS is also stored in the same ROM ...

Page 11: ... 000E0000 000FFFFF Conventional Memory 00000000 00100000 FFFC0000 FFFFFFFF 4000000 α BIOS ISA Reserved Memory S DRAM 1 S DRAM 2000000 α 1 Memory size can be 32MB or 64MB depending on the model 2 With some types of Video C0000h to CBFFFh can be occupied as VIDEO BIOS α Area for the video memory Max 4MB Figure 1 3 Memory map ...

Page 12: ...Address 05h RW DMA Channel 2 Base and Current Word 06h RW DMA Channel 3 Base and Current Address 07h RW DMA Channel 3 Base and Current Word 08h WO Command Resister 08h RO Status Register 09h WO Request Register 0Ah WO Single Mask Register 0Bh WO Mode Register 0Ch WO Clear Byte Pointer 0Dh RO Master Clear 0Dh WO Temporary Register 0Eh WO Clear Mask Register 0Fh WO Write all Mask Register 020h 021h ...

Page 13: ...roller Data Output Buffer Keyboard Controller 61h RW Port B 62h RW Keyboard controller mailbox Register 64h WO Keyboard controller Command Register 060h 06Fh 64h RO Keyboard Controller Status Register Keyboard Controller 070h 07Fh 70h WO RTC CMOS RAM Address Port and NMI Mask 71h RW RTC CMOS RAM Data port RTC CMOS RAM 080h 09Fh 80h RW Reserved 81h RW Channel 2 82h RW Channel 3 83h RW Channel 1 84h...

Page 14: ...ter C0h RW DMA Channel 4 Base and Current Address C2h RW DMA Channel 4 Base and Current Word 0C0h 0DFh C4h RW DMA Channel 5 Base and Current Address C6h RW DMA Channel 5 Base and Current Word C8h RW DMA Channel 6 Base and Current Address CAh RW DMA Channel 6 Base and Current Word CCh RW DMA Channel 7 Base and Current Address CEh RW DMA Channel 7 Base and Current Word D0h W0 Command Register D0h RO...

Page 15: ... Register 1F8h 277h UsablewithISAbus 278h 27Fh 278h RW LPT2 Data Port 279h RO LPT2 Status Port Parallel Port 2 27Ah RW LPT2 Control 27Bh RW Automatic Address Strobe Register 27Ch RW Automatic Data Strobe Register 27Dh RW Automatic Data Strobe Register 27Eh RW Automatic Data Strobe Register 27Fh RW Automatic Data Strobe Register 280h 2F7h UsablewithISAbus 2F8h 2FFh 2F8h RO Receiver Buffer 2F8h WO T...

Page 16: ...put Status Register 3BBh 3BFh UsablewithISAbus 3C0h 3CFh 3C0h W Attribute Controller Index Data 3C1h R Attribute Controller Index Data VGA Controller 3C2h W Miscellaneous Output 3C2h R Input Status Register 3C3h RW VGA Enable 3C4h RW Sequencer Index 3C5h RW Sequencer Data 3C6h RW Video DAC Pixel Mask Hidden DAC Register 3C0h 3CFh 3C7h W Pixel Address Read Mode 3C7h R DAC Status VGA Controller 3C8h...

Page 17: ...h 3F7h RO Digital Input Resister Shared with Hard Disk Controller IDE 1 section FDD 3F7h WO Diskette Control Register FDD Controller 3F8h 3FFh 3F8h RO Receiver Buffer 3F8h WO Transmit holding Buffer Serial Port 1 3F8h RW Divider Latch Least Significant Byte 3F9h RW Divider Latch Most Significant Byte 3F9h RW Interrupt Enable Register 3FAh RO Interrupt ID Register 3FBh RW Line Control Register 3FCh...

Page 18: ... cannot be used by user CH7 Not available cannot be used by user Controller 1 including CH0 to CH3 is used for 8 bit data transfer Up to 64KB block transfer is possible between 8 bit I O and 8 bit memory or 16 bit memory Controller 2 including CH4 to CH7 is mainly used for 16 bit data transfer and among them CH4 is used for cascade connection of controller 1 CH5 to CH7 are not used Controller 2 in...

Page 19: ...er Controller 1 Controller 2 Device IRQ0 Timer out 0 IRQ1 Keyboard IRQ2 Cascade connection from controller 2 IRQ8 Real time clock IRQ9 Usable with ISA bus IRQ10 Serial port IRQ11 Serial port IRQ12 Mouse IRQ13 Co Processor IRQ14 HDD IRQ15 Usable with ISA bus IRQ3 Serial port 2 IRQ4 Serial port 1 IRQ5 Parallel port 2 IRQ6 FDD IRQ7 Parallel port 1 SCE8720C has 2 serial ports and 1 parallel port built...

Page 20: ...own below Table 1 7 Timer 1 settings Channel 0 GATE 0 Fixed to ON System timer CLK IN 0 1 19MHz CLK OUT 0 Connected to IRQ0 of interrupt controller 1 Channel 1 GATE 1 Fixed to ON Refresh request CLK IN 1 1 19MHz CLK OUT 1 Refresh request Channel 2 GATE 2 Controlled by I O port 61h Speaker interface CLK IN 2 1 19MHz CLK OUT 2 Used to drive the speaker interface ...

Page 21: ...onfiguration information The real time clock is compatible with 146818 Power must be supplied constantly to the VCCBAK in order to maintain the operation of the real time clock and the contents of CMOS RAM When VCCSTB is supplied even while the system power is OFF power from the VCCSTB is used for backup When both the system power and VCCSTB is OFF battery power from the VCCBAK is used ...

Page 22: ...th 63 5 0 3 mm Height 16 0 1 0 mm Weight Approx 82g Figure 2 1 Dimensional Diagram 2 2 Installation method CARD PCI installation connector 280 pin connector product name 1 353906 0 Manufactured by AMP 20 pin connector product name52030 2010 ZIF DIP Manufactured by Molex For more information about installation refer to the application note 101 6 1 0 63 5 0 3 Heat sink Main board 3 M2 screw uniqro 8...

Page 23: ...is connected using the flexible flat cable FFC pin configurations on the receiving side board vary depending on the connector s installation method 20 pin connector Rear side 1 20 1 140 2 139 69 72 70 71 141 280 142 279 209 212 210 211 141 280 142 279 209 212 210 211 1 140 2 139 69 72 70 71 Receiver side board Parts side Flexible flat cable SCE8720C 280 pin connector Rear side Figure 3 1 Connector...

Page 24: ...DEDRQ IDE 33 RESERVED MISC 108 LPTD3 LPT 173 RESERVED MISC 248 IDERDY IDE 34 IRDY PCI 107 LPTD2 LPT 174 RESERVED MISC 247 IDEINT IDE 35 VCC3V P W R 106 VCC3V P W R 175 VCCCORE P W R 246 POWERGOODPM 36 FRAME PCI 105 LPTD1 LPT 176 VCCCORE P W R 245 IOCS16 ISA 37 PME0 PM 104 LPTD0 LPT 177 VCCCORE P W R 244 IOCHRDY ISA 38 CBE2 PCI 103 LPTAFD LPT 178 VCCCORE P W R 243 VCCCORE P W R 39 AD16 PCI 102 LPTS...

Page 25: ... 20 pin connector pin configuration Pin No Signal name Block 1 DSKCHG FDD 2 WP FDD 3 INDEX FDD 4 TRK0 FDD 5 RDATA FDD 6 DENSEL FDD 7 WGATE FDD 8 HDSEL FDD 9 STEP FDD 10 DIR FDD 11 WDATA FDD 12 DR0 FDD 13 MTR0 FDD 14 GND PWR 15 IRQ15 ISA 16 IRQ 7 ISA 17 GND PWR 18 IRQ4 ISA 19 GND PWR 20 IRQ3 ISA ...

Page 26: ... input Output Indicates the voltage level that can be output pull up down Indicates whether or not the signal is pulled up or pulled down inside SCE8720C IOL IOH Indicates drive ability of the output buffer sink current and source current Reference PU PD Reference value of required pull up or pull down resistance When using all the IO port pull up down when not used Indicates whether or not pull u...

Page 27: ... input and output is 0 to 5 0V 5V input is TTL level XpU 5V Pulled up to 5V by resistance of xΩ inside SCE8720C xPU 3 3V Pulled up to 3 3V by resistance of x Ω inside SCE8720C xPU 5VSTB Pulled up to VCCSTB by resistance of x Ω inside SCE8720C xPD Pulled down by resistance of x Ω inside SCE8720C weak PU Pulled up to 5V by Approx 40kΩ resistance pull up down Weak PD Pulled down by Approx 40kΩ resist...

Page 28: ...O 3 3V 5mA 2mA PCLK 2 0 3 PCI O 3 3V 8mA 8mA INTA INTB INTC INTD 4 PCI I 3 3V 2 7kPU 3 3V PU Table 3 4 ISA signal characteristics Signal name 280 pin connector No of pins Block I O Vol tage IOL IOH Reference PU PD Whennotused PU PD SD SA 15 8 8 ISA I O 3 3V 5VT 20kPU 3 3V 8mA 8mA SD SA 7 0 8 ISA I O 3 3V 5VT 20kPU 3 3V 8mA 8mA 4 7kPU 5V SA 19 16 SBHE 5 ISA O 3 3V 20kPU 3 3V 8mA 8mA MEMR MEMW IOR I...

Page 29: ...EACK IDECS1FX IDECS3FX IDERESET 9 IDE O 3 3V 8mA 8mA IDERDY 1 IDE I 3 3V 5VT 1kPU 5V IDEINT IRQ14 1 IDE I 3 3V 5VT 10kPU 5V IDEDRQ 1 IDE I 3 3V 5VT 10kPD Table 3 7 USB signal characteristics Signal name 280 pin connector No of pins Block I O Vol tage IOL IOH Reference PU PD Whennotused PU PD USBDM1 USBDP1 USBDM0 USBDP0 4 USB I O 3 3V 15kPD USBON 1 USB O 3 3V 4mA 4mA USBCUR 1 USB I 3 3V 5VT 10kPU 5...

Page 30: ...mA 2kPU 5V PU Table 3 11 AC97 signal characteristics Signal name 280 pin connector No of pins Block I O Vol tage IOL IOH Reference PU PD Whennotused PU PD AC97SDIN0 AC97BITCLK 2 AC97 I 3 3V 5VT 15kPD AC97SDOUT AC97SYNC PCBEEP 3 AC97 O 3 3V 4mA 4mA AC97RESET 1 AC97 O 3 3V 16mA 16mA Table 3 12 PM signal characteristics Signal name 280 pin connector No of pins Block I O Vol tage IOL IOH Reference PU ...

Page 31: ... pin connector No of pins Block I O Vol tage IOL IOH Reference PU PD Whennotused PU PD GND 3 Power supply 0V 20 total 1 Circuits corresponding these signals are essential and therefore cannot be unused 2 If the ports corresponding to these signals in SCE8720C are set to output pull up resistance is not necessary If the ports are set to input pull up resistance is necessary 3 When set to NC the ROM...

Page 32: ... AD 31 0 and CBE 3 0 FRAME S T S Signal indicating the cycle frame IRDY S T S Ready signal of the initiator TRDY S T S Ready signal of the target STOP S T S Signal from target requesting transaction canceleration DEVSEL S T S Signal from the PCI slave indicating that it is selected LOCK S T S Signal used when exclusively accessing the target SERR I OD Signal indicating that a fatal error has occur...

Page 33: ...ress enable Signal which indicates that the current cycle is DMA or refresh cycle SBHE O System byte enable Active low Signal which indicates that SD 15 8 is enabled ROMCS O Signal which becomes active at ROM access Active low MEMR O Memory read Active low Signals which request the memory device on the ISA bus to output data to SD 15 8 or SD 7 0 This gets active when the memory address area on the...

Page 34: ...SCE8720C that 16 bit transfer is possible by the current I O cycle IOCHRDY I I O channel ready Active high Signal which terminates the ISA bus cycle When the memory or the I O device on the ISA bus wants to extend the bus cycle it can extend the cycle by setting this signal to low immediately after detecting an effective address and command SCE8720C continues the bus cycle until this signal become...

Page 35: ...omes output When being not used they become inputs and can be used on the ISA bus 3 3 3 LCD With SCE8720C only TFT panel can be used as LCD panel STN panel cannot be used LCD data is 18 bit FPDATA17 0 Signal name 25 pins in total I O Function description FPHSYNC FPVSYNC O Horizontal and vertical synchronous signals for flat panel TFT FPDATA 17 0 O Dot data for flat panel TFT 6 bits for R G and B e...

Page 36: ...S1FX IDECS3FX O Chip select signal for IDE IDERDY I IO ready signal for IDE IDEINT IRQ14 I IDE interrupt signal IDEDRQ I DMA transfer request signal for IDE IDEACK O DMA acknowledge signal for IDE IDERESET O Reset signal for IDE No pull up resistance is required for IDE 15 0 3 3 6 USB SCE8720C supports 2 ports of USB complying with the Open HCI Signal name 6 pins in total I O Function description ...

Page 37: ...ata transmission with respect to SCE8720C COM1RTS COM2RTS O Request to send Active low Signal which indicates that SCE8720 has transmission data ready and indicates a request to transmit data with respect to the modem or data terminal COM1CTS COM2CTS I Clear to send Active low Signal which indicates that the modem or data terminal has become ready to receive for the SCE8720C s request to send COM1...

Page 38: ...printer acknowledge Active low Signal which indicates that data transfer has been completed and also prepared for the next transfer LPTERROR I Line printer error Active low Input signal which notifies SCE8720C of errors in peripheral devices LPTPE I Line printer paper end Active high Input signal which notifies SCE8720C that the printer is out of paper LPTINIT I OD Line printer initialize Active l...

Page 39: ...ector Pin No Signal name SPP ECP EPP 1 LPTSTROBE LPTSTROBE LPTSTROBE WRITE 2 9 LPTD 7 0 LPTD 7 0 LPTD 7 0 LPTD 7 0 10 LPTACK LPTACK LPTACK LPTACK 11 LPTBUSY LPTBUSY LPTBUSY WAIT 12 LPTPE LPTPE LPTPE LPTPE 13 LPTSLCT LPTSLCT LPTSLCT LPTSLCT 14 LPTAFD LPTAFD LPTAFD DSTRB 15 LPTERROR LPTERROR LPTERROR LPTERROR 16 LPTINIT LPTINIT LPTINIT LPTINIT 17 LPTSLCTIN LPTSLCTIN LPTSLCTIN ASTRB ...

Page 40: ...ata signal for a PS 2 style mouse interface 3 3 10 AC97 interfaces SCE8720C provides audio CODEC interface complying AC97 Version 2 0 By adding CODEC and using the dedicated driver high quality audio is easily achieved There s only 1 channel for AC97 serial data Signal name 6 pins in total I O Function description AC97SDIN0 I Audio serial data input from CODEC AC97SDOUT O Audio serial data output ...

Page 41: ...gnal which represents standby status Standby at LOW POWERGOOD I Input power good signal which indicates that the power is properly supplied When this signal is LOW the card is initialized PME1 I Wake on RING input PME0 I Power management input signal usually assigned to Wake on LAN signal PORT4 programmable General purpose input output signal GPIO13 of PC97317 PORT3 programmable General purpose in...

Page 42: ...nal supplied to the power supply control circuit inside the card Power of 5V is always supplied when AC line of the power supply is connected VCCBAK power supply for RTC backup 3 3 13 FDD SCE8720C supports 1 unit of 3 5 floppy disk drive 2 modes 720KB and 1 44MB are available Signal name I O Function description DSKCHG I Disk Change WP I Write Protect INDEX I Index TRK0 I Track 0 RDATA I Read Data...

Page 43: ...poration Display resolution and No of colors of CRT and TFT are as follows Adjustment of display frequency and position to suit the panel must be done from the utility software Table 3 16 TFT display mode Resolution No of colors Panel type 9 bits 12 bits 8BPP 256 colors from palette 18 bits 9 bits 12 bits 640 480 16BPP 64K colors R 5 bits G 6 bits and B 5 bits 18 bits 9 bits 12 bits 8BPP 256 color...

Page 44: ...alette Connection method of TFT signal and panel is shown below R5 Red MSB G5 Green MSB B5 Blue MSB Table 3 18 TFT display data assignment 9 bit TFT Signal name 18 bit TFT 12 bit TFT 640 480 1024 768 FPDATA17 R5 R5 R5 R5 FPDATA16 R4 R4 R4 R4 FPDATA15 R3 R3 R3 R3 Even pixel FPDATA14 R2 R2 R5 FPDATA13 R1 R4 FPDATA12 R0 R3 Odd pixel FPDATA11 G5 G5 G5 G5 FPDATA10 G4 G4 G4 G4 FPDATA9 G3 G3 G3 G3 Even p...

Page 45: ... below If secondary IDE is needed extend to the ISA bus SCE8720C IDE IDED15 0 IDEA2 0 IDEIOR IDEIOW IDECS1FX IDECS3FX IDERDY IDEINT IRQ14 IDEDRQ IDEACK IDERESET D15 0 A2 0 IOR IOW CS1FX CS3FX RDY INT IRQ14 DRQ DACK RESET Figure 4 1 IDE interface connection Each signal of IDE can be directly connected to IDE with no problem However it is sometimes better to add serial dumping resistances of 33Ω or ...

Page 46: ...e available Connection method of FDD is shown below SCE8720C 3 5 FDD DSKCHG WP INDEX TRK0 RDATA DENSEL WGATE HDSEL STEP DIR WDATA DR0 MTR0 DSKCHG WP INDEX TRK0 RDATA DENSEL WGATE HDSEL STEP DIR WDATA DR0 MTR0 5V 4 7kΩ 8 Resistance of 4 7kΩ 8 is not necessary when built into FDD Figure 4 2 FDD interface connection ...

Page 47: ...2 type keyboard and mouse Connection method is shown below SCE8720C 5V KBDATA KBCLK MSDATA MSCLK Keyboard Mouse 4 7K 2 5 4 7K 2 5 Figure 4 3 Keyboard mouse interface connection All the keyboard and mouse signals require pull up resistance of 4 7kΩ or so Pull up resistance of 100kΩ or so is required even when not in use ...

Page 48: ...face connection All the parallel port signals require pull up resistance of 4 7kΩ or so Even when the parallel port is not in use the LPTD 7 0 LPTINIT LPTSTROBE PTAFD LPTSLCTIN signals require pull up resistance of 100kΩ or so The diode in the dotted rectangular is for preventing troubles from happening due to current flowing from the printer signal to the 5V of the system when the power of the sy...

Page 49: ... SCE8720C directly to the USB connector 2 channel USB port becomes available When the overcurrent detector of the USB detects an overcurrent USB port can be disabled in order to protect the circuit In this case even if only one port is detected as an overcurrent both USBs are disabled Connection example is shown below Overcurrent detector USB ch1 USB ch0 USBON USBCUR USBDP1 USBDM1 USBDP0 USBDM0 5V...

Page 50: ...720C Figure 4 6 Piezoelectric buzzer connection 4 9 PCI PCI bus of SCE8720C complies with the PCI2 1 but the power voltage is limited to 3 3V Up to 3 PCI devices can be connected also limited by the number of PCICLKs Among these up to 2 PCI devices can be connected as master limited by the numbers of REQ and GNT If you wish to connect a 5V PCI device or PCI devices of more than 3 refer to the refe...

Page 51: ...an be generated from other signals 6 SCE8720C s ISA output is 3 3V max Since the IC power supply which drives the ISA bus is 3 3V SCE8720C s ISA output level is 3 3V maximum Input signal level is 5V tolerant 7 IRQ5 9 10 and 11 for the 280 pin connector and IRQ3 4 7 and 15 for the 20 pin connector are supported Reference 8 2 IO extension of ISA bus 4 11 RTC MC146818A compatible RTC function is buil...

Page 52: ...dby mode In standby mode the display is turned OFF and the peripheral devices also get into the power saving mode motors of HDD and FDD are turned OFF To return to the standard operation mode from the standby mode the power switch input within 4 seconds or keyboard mouse input is effective However whether or not the operation mode is resumed is determined by the BIOS settings 5 3 Power supply VCC3...

Page 53: ...CARD PCI GX Hardware Manual EPSON Rev A 48 VCCBAK Supplied in order to maintain the RTC and C MOS RAM when no VCCSTB is supplied as the power is OFF ...

Page 54: ...CC3V or if VCCORE shuts down before VCC3V peak current such as IPK is supplied to VCC3V typical IPK 1 8A As a system power supply it must be designed so that it is not damaged if a peak current is supplied For that the following measures are available 1 Suppress the peak current from the current control circuit Voltage drop due to this measure is acceptable 2 Increase the current capacity 0 33V 0 ...

Page 55: ...4 75V to POWERGOOD active 10 ms tp4 VCC3V 3 15V to POWERGOOD active 10 ms tp5 POWERGOOD inactive to VCCCORE VCC5V 4 75V 0 ms tp6 POWERGOOD inactive to VCC3V 3 15V 0 ms tp7 VCCCORE VCC5V rise time 20 ms tp8 VCC3V rise time 20 ms tp9 VCCCORE VCC5V 4 75V to VCC3V 0 33V 100 80 ms tp10 Width of POWERGOOD 10 tp11 VCCSTB 4 5V to POFF inactive 500 tp12 POFF active to VCCSTB 4 5V 500 ms ...

Page 56: ...er VCC3V or if VCCORE shuts down before VCC3V peak current such as IPK is supplied to VCC3V typical IPK 1 8A As a system power supply it must be designed so that it is not damaged if a peak current is supplied For that the following measures are available 1 Suppress the peak current from the current control circuit Voltage drop due to this measure is acceptable 2 Increase the current capacity 3 Co...

Page 57: ... Voltage VCCBAK 0 5 6 5 V CPUFRQ 0 5 VCC3V 0 5 V PCLK 2 0 0 5 VCC3V 0 5 V Votage on pin Other pins 0 5 1 V 1 Lower voltage between 5 5V and VCC5V 0 5V 6 2 Recommended operating condition Symbol Min Max Unit Current Limit 2 VCCCORE 4 75 5 25 V 2 5A VCC5V 4 75 5 25 V VCC3V 3 15 3 45 V 3A VCCSTB 4 5 5 5 V VCCBAK 2 7 3 6 V 2 Even if any part defect occurred in SCE8720Cxx do not supply current over the...

Page 58: ...IRDY TRDY STOP LOCK DEVSEL PERR SERR and REQ 2 0 signals 6 3 2 LIMITED ISA bus Symbol Parameter Condition Min Max Unit Note VIL Input low voltage 0 3 0 8 V VIH Input high voltage 2 0 VCC5V V VOL1 Output low voltage IOL 8mA 0 4 V 1 VOL2 Output low voltage IOL 4mA 0 4 V 2 VOH1 Output high voltage IOL 8mA 2 4 V 1 VOH2 Output high voltage IOL 4mA 2 4 V 2 ILL1 Input leakage current VIN 0 35V 400 µA 3 I...

Page 59: ...TCH AEN and ROMCS 6 3 3 LCD Symbol Parameter Condition Min Max Unit Note VOL Output low voltage IOL 8mA 0 4 V VOH Output high voltage IOH 8mA 0 4 V 6 3 4 CRT Symbol Parameter Condition Min Max Unit Note VOL1 Output low voltage IOL 16mA 0 4 V 1 VOH1 Output high voltage IOH 16mA 2 4 V 1 VOL2 Output low voltage V 2 VOH2 Output high voltage V 2 1 CRTHSYNC CRTVSYNC 2 CRTR CRTG CRTB ...

Page 60: ...meter Condition Min Max Unit Note VIL Input low voltage 0 3 0 8 V 1 VIH Input high voltage 2 0 VCC5V V 1 VOL Output low voltage IOL 8mA 0 4 V 2 VOH Output high voltage IOH 8mA 2 4 V 2 ILL1 Input leakage current VIN VCC5V 5 5 mA 3 ILL2 Input leakage current VIN VCC5V 5 5 mA 4 ILL3 Input leakage current VIN VSS 5 5 mA 5 ILL4 Input leakage current VIN VSS 550 µA 6 ILL5 Input leakage current VIN VCC5V...

Page 61: ...rallel port Symbol Parameter Condition Min Max Unit Note VIL Input low voltage 0 5 0 8 V 1 VIH Input high voltage 2 0 VCC5V V 1 VOL Output low voltage IOL 14mA 0 4 V 2 VOH Output high voltage IOH 14mA 2 4 V 2 ILL1 Input leakage current VIN VSS 10 µA 3 ILL2 Input leakage current VIN VSS 120 µA 4 ILL3 Input leakage current VIN VCC5V 120 µA 3 ILL4 Input leakage current VIN VCC5V 10 µA 4 1 All the par...

Page 62: ...USBON 3 USBDM1 USBDP1 USBDM0 USBDP0 1 5kΩ of pull up resistance is added outside SCE8720C 4 USBDM1 USBDP1 USBDM0 USBDP0 15kΩ of pull up resistance is added outside SCE8720C 6 3 11 Power management signal PME0 signal For compatibility with other cards input should be set to low or high impedance Symbol Parameter Condition Min Max Unit Note VIL Input low voltage 0 5 0 8 V VIH Input high voltage 2 V ...

Page 63: ...nput high voltage 2 2 V ILL1 Input leakage current VIN VCC5V 10 µA ILL2 Input leakage current VIN VSS 1 2 mA POFF signal open collector Symbol Parameter Condition Min Max Unit Note VOL1 Output low voltage IOL 14mA 0 4 V STANDBY signal Symbol Parameter Condition Min Max Unit Note VOL1 Output low voltage IOL 16mA 0 4 V 6 3 12 AC97 Symbol Parameter Condition Min Max Unit Note VIL Input low voltage 0 ...

Page 64: ...put high voltage 2 0 VCC5V V VOL Output low voltage IOL 14mA 0 4 V VOH Output high voltage IOH 2mA 2 4 V ILL1 Input leakage current VIN VCC5V 10 µA ILL2 Input leakage current VIN VSS 550 µA CPUFRQ signal this signal is not 5V tolerant Symbol Parameter Condition Min Max Unit VIL Input low voltage 0 3 VCC3V V VIH Input high voltage 0 7 VCC3V V ILL1 Input leakage current VIN VCC3V 3 6 mA ILL2 Input l...

Page 65: ...nit Note VCCCORE 1 500 750 mA VCCCORE 5V VCC5V 1 20 30 mA VCC5V 5V VCC3V 2 640 960 mA VCC3V 3 3V VCCSTB 1 1 5 mA VCCSTB 5V Current VCCBAK 1 2 µA VCCBAK 3V Power total 4717 7075 5 mW 1 At Windows 98 startup 2 Screen saver pipe 6 4 2 Typical current value 1 Measurement method Startup Windows 98 and measure while nothing is being executed by the application APM Advanced Power Management OFF Memory si...

Page 66: ...4MB Display 1280 1024 256 color CRT Item Symbol Typ Unit Note VCCCORE 110 mA VCCCORE 5V VCC5V 17 1 mA VCC5V 5V VCC3V 530 mA VCC3V 3 3V VCCSTB 0 35 mA VCCSTB 5V Current VCCBAK 0 µA VCCBAK 3V Power total 2386 3 Mw 6 4 4 Standby current Measurement method Measure in the standby mode Memory size 64MB Item Voltage Typ Unit Note VCCCORE 17 2 mA VCCCORE 5V VCC5V 11 5 mA VCC5V 5V VCC3V 230 mA VCC3V 3 3V V...

Page 67: ...tion 2 1 for details 7 2 USB timing Since the PCI timing is based on the PCI BUS Specification rev2 1 refer to the PCI BUS Specification 2 1 for details 7 3 LIMITED ISA timing ISA signals comply with the ISA specifications 7 3 1 Memory I O read cycle timing Figure 7 1 Memory I O read cycle timing t5 t7 t9 t13 t17 AEN SA 19 16 SBHE ROMCS MEMCS16 IOCS16 MEMR IOR SALATCH SD SA 15 0 IOCHRDY t1 t2 t3 t...

Page 68: ...0 Memory read command pulse width 209 ns 16 bits 509 ns 8 bits t10 IO read command pulse width 147 ns 16 bits t11 SA 19 16 to falling edge of SALATCH 28 ns t13 SA onSD SA active to SALATCH inactive 13 ns t14 SA onSD SA inactive to SALATCH inactive 5 ns 460 ns 8 bits t15 Valid read DATA from M read command 161 ns 16 bits 462 ns 8 bits t15 Valid read DATA from I read command 103 ns 16 bits t16 Read ...

Page 69: ...Figure 7 2 Memory I O write cycle timing Symbol Parameter Min Max Unit Note 162 ns 8 bits t30 Write Command active from SA 19 16 102 ns 16 bits 509 ns 8 bits t31 Memory write command pulse width 209 ns 16 bits 509 ns 8 bits t31 IO write command pulse width 147 ns 16 bits 61 ns 8 bits t32 Write data valid from write command 47 ns 16 bits t33 Valid data from write command 25 ns ...

Page 70: ... BITCLK to SYNC 5 16 ns tsdat Rising BITCLK to SDOUT 5 17 ns tsdatsetup SDIN0 setup to falling BITCLK 15 ns tsdathold SDIN0 hold from falling BITCLK 5 ns 7 5 TFT timing Figure 7 4 TFT timing Symbol Parameter Min Max Unit Note tfpoutmin Min Delay tfpoutmax Max Delay TFT output Delay from FPDOTCLK FPDATA 17 0 FPHSYNC FPVSYNC FPDISPEN FPDOTE FPVEEON FPVDDON 0 1 5 2 ns FPDOTCLK TFT output tfpoutmin tf...

Page 71: ... cover so that SCE8720Cxx cannot be touched 2 If any part defect occurred in SCE8720Cxx do not supply current over the current limit 6 1 1 in order to suppress abnormal heating of SCE8720Cxx If current over the current limit is supplied to SCE8720Cxx while it is in the error mode safety of SCE8720Cxx cannot be guaranteed 3 Because of its structural limitation SCE8720Cxx requires countermeasure aga...

Page 72: ...his case it is necessary to confirm the waveform of PCICLK using an actual circuit Also determine whether or not a terminal circuit of PCICLK is needed Since loads of other signals are also increased these signals must be checked as well When using divided PCICLK do not use PCICLK for the extended slot More than 1 device might be connected in a board Connected to extended slot Note that customizat...

Page 73: ...ample of interrupt and IDSEL is shown in the figure below Table A 1 PCI device No assignment PCI device IDSEL Device No Chipset inside Geode CS5530 AD28 18 12h USB inside Geode CS5530 AD29 19 13h PCI device 1 AD24 14 Eh PCI device 2 AD25 15 Fh PCI device 3 AD26 16 10h Wire the interrupt cables for each slot so that load is put equally on each of INTA to INTD on the PCI device Customization of BIOS...

Page 74: ...CI bus cannot be connected to the PCI bus To connect a 5V PCI device use the level converter which converts signals from 5V device to 3 3V as shown in the circuit below Figure A 3 Connection method of 5V PCI device CARD PCI PCICLK PCICLK 3V PCI 5 RN5RL43A Eg quality semiconductor QS32X245 VCC Level conver ter 5V PCI device 4 3V regulator ...

Page 75: ... outside SCE8720C are the ones not used by the system within the range from 100h to 3FFh refer to the IO map in the section 1 6 When decoding the conditions SA0 9 and AEN 0 must be set to input A 2 2 Pull up of SD SA 7 0 Pull up SD SA 7 0 by a resistance of 4 7kΩ or so Otherwise the software cannot detect empty space in the memory area ...

Page 76: ...TTL and wiring length Therefore design must be done by calculating the load wiring length fine in and fine out refer to 6 3 A 2 5 Pull up resistance of IOCHRDY Since IOCHRDY sample timing is fixed devices on the ISA must change the signal within the fixed timing This signal might be delayed due to increased load capacity so externally add a pull up resistance when load is heavy Of course this resi...

Page 77: ...MEMW SMEMR SMEMW Figure A 6 Circuit to generate SMEMR and SMEMW A 2 7 MEMCS16 generation To generate MEMCS16 the condition ROMCS 1 BIOS ROM is not selected is necessary If this condition is absent error such as improper overwrite on BIOS ROM might occur Circuit example is shown below Figure A 7 Circuit to generate ROMCS16 MEMCS16 is active at D0000 to DFFFF ALS138 0 A 1 B 2 C 3 G1 4 G2A 5 G2B 6 7 ...

Page 78: ...ing down Wake on LAN nor Wake on RING power control is much easier not requiring VCCSTB Block diagram is shown below If the power ON OFF switch cannot be used as the switch to suspend the switch to suspend is separately required Power supply unit Eg AT power supply POWERGOOD signal of the power supply CARD PCI VCCSTB Powergood POFF PWSW STANDBY PME0 PME1 Reset circuit ON OFF SW 3 3V Suspend LED NC...

Page 79: ...wn for less than 4 seconds while the power is on it transits to the suspend status Holding down the switch for more than 4 seconds the power is turned off In this case a separate suspend switch is not necessary Figure A 8 Example of peripheral circuit for power controlled by software Power supply unit Eg ATX power supply Reset circuit Wake on LAN Wake on RING circuit CARD PCI VCCSTB Powergood POFF...

Page 80: ...GH LOW at 3 3V Therefore design the circuit to support both as shown in Figure A 7 and A 8 A 3 4 Wake on LAN signal PME0 signal is used for Wake on LAN With PCI version 2 2 this signal is assigned to A19 pin of the PCI option connector However SCE8720C s PCI is version 2 1 so do not connect PME0 signal to the PCI connector For Wake on LAN using PME0 signal use another connector There are connector...

Page 81: ...F ceramic capacitor 1 Large quantity 3 VCCSTB GND 10µF 10V electrolytic capacitor 0 01µF ceramic capacitor 1 2 3 VCCBAK 1µF laminated ceramic 1 1 VCCORE is input voltage of DC DC converter which generates the core voltage 2 2V of CPU Although SCE8720C has a built in capacitor another capacitor is needed on the system side as peak current flows anyway Since the voltage is 5V it is possible to use t...

Page 82: ...ng the PCI signal wiring too long since the PCI signal speed is higher than those of ISA If long wiring cannot be avoided or load is heavy be sure to confirm the waveform A 4 4 Clock signal High speed clock signal are likely to negatively affect other signals by crosstalk or be affected by other signals resulting in trouble To avoid such troubles guard it using GND patter as shown below GND via Si...

Page 83: ...rosstalk occurs A 4 6 Reset signal Use the RST signal for resetting the system other than SCE8720C Do not make the signal wiring too long If long wiring cannot be avoided add a buffer or a capacitor to remove noise Also POWERGOOD signal should not be used to reset the system circuit other than SCE8720C This is fine from the logical viewpoint but it does raise the possibility to extract noise resul...

Page 84: ...les of power management signals 1 Powering ON by PWSW or PME0 1 Powering OFF by PWSW Figure B 1 PM signal operation timing example 1 2 Transit to from the standby mode by PWSW Note Do not supply VCC5V when VCCSTB is OFF Figure B 2 PM signal operation timing example 2 VCCSTB VCC5V VCCORE VCC3V POFF POWERGOOD PWSW PME 0 1 Supply Supply 4S 4S VCCSTB VCC5V VCCORE VCC3V POFF POWERGOOD PWSW STANDBY Supp...

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Page 86: ...ursuit of Saving Technology Epson electronic devices Our lineup of semiconductors liquid crystal displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 87: ...CARD PCI GX Hardware Manual SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Devices Information On Epson WWW server http www epson co jp device Printed July 2000 in Japan H A ...

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