ICS PCI-WDT 500, Product Manual

Page: 43 / 44

Manual Number: 00650-144-1 Page 30
PCI-WDT 500/501 Manual
The readback command byte format is:
7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 B
1 1 T N C A T S 2 C 1 C 0 C 0
CNT: When is 0, latches the counters selected by bits C0-C2.
STA: When is 0, returns the status byte of counters selected by C0-C2
C0,C1,C2: When high, select a particular counter for readback. C0 selects Counter 0,
C1 selects counter 1, and C2 selects counter 2.
You can perform two types of readback operations with the readback command. When CNR=0, the
counters selected by C0-C2 are latched simultaneously . When STA=0, the counter status byte is
read when the counter I/O location is accessed. The counter status byte provides information about
the current output state of the selected counter and its configuration. The status byte returned if
STA=0 is:
7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 B
T U O C N 1 W R 2 W R 2 M 1 M 0 M D C B
OUT: Current state of counter output pin.
NC: Null count. This indicates when the last count loaded into the counter
register has actually been loaded into the counter itself. The exact time of
load depends on the configuration selected. Until the count is loaded into
the counter itself, it cannot be read.
RW0 and RW1: Read/Write command.
M0-M2: Counter mode.
BCD: BCD=0 sets binary mode, otherwise counter is in BCD mode.
If STA and CNT bits in the readback command byte are set low and the RW1 and RW0 bits have
both been previously set high in the counter control register (thus selecting two-byte reads), then
reading a counter address location will yield:
1st Read: Status byte
2nd Read: low byte of latched data
3rd Read: High byte of latched data.
After any latching operation of a counter, the contents of its hold register must be read before any
subsequent latches of that counter will have any effect. If a status latch command is issued before
the hold register is read, then the first read will read the status, not the latched value.