ICS Advent PCI-DIO32, User Manual

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Technical Description 3-7
Table 3-3. Register Description
Note: All ports are set to input after reset or power up. Interrupt source is
Base+0 bit D0. When selecting the Interrupt Mode, always disable
interrupts before changing or setting states, to prevent inadvertent or
unexpected interrupts. When using the high and low level interrupts,
a change in state of the input must occur before the interrupt can be
cleared. The device providing the input to Base+0 bit D0 must
do this.
IRQEN = enable interrupts (Base+5)
0 = disabled 1 = enabled (disabled after reset or power up)
IRQST = interrupt status (Base+5)
1 = interrupt pending (reading the bit clears interrupt)
Address Mode D7 D6 D5 D4 D3 D2 D1 D0
Base+0 RD/
WR PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0
Base+1 RD/
WR PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0
Base+2 RD/
WR PCD7 PCD6 PCD5 PCD4 PCD3 PCD2 PCD1 PCD0
Base+3 RD/
WR PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0
Base+4 RD/
WR {0} {0} {0} {0} {0} {0} {0} {0}
Base+5 RD/
WR IRQE
N
IRQS
T
{0} {0} {0} {0} IRC1 IRC0
Base+6 RD
Only
{0} {0} {0} {0} {0} {0} {0} {0}
Base+7 RD
Only
{0} {0} {0} {0} {0} {0} {0} {0}
PAD0–7 = Port A (Base+0)
PBD0–7= Port B (Base+1)
PCD0–7 = Port C (Base+2)
PDD0–7 = Port D (Base+3) IRC0 and IRC1 = Interrupt Mode select Base+5)
IRC1
0
0
1
1
IRC0
0
1
0
1
low level
high level
falling edge
rising edge