E - 4 - 5
4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC-R/LOGIC-T UNITS; IC50)
Pin
number
Port
name
Description
42
TXD1
Output data signals to the USB con-
trollers (IC550, pin 24).
43
RXD1
Input port for data signals from the
USB controllers (IC550, pin 25) via
the (IC553).
53
SDA
I/O port for data signals from/to the
EEPROMs (IC54, pin 5).
54
SCL
Outputs clock signal to the EEPROMs
(IC54, pin 6).
71
RESET
Input port for reset signal form the re-
set ICs (IC52, pin 1).
72
P2RSC
Outputs control signal to the mode
switches (MAIN-R/MAIN-T units;
IC551, pin 5) via the level converter
(IC55).
73
P2STC
Outputs strobe signal to the 2nd PLL
ICs (MAIN-R/MAIN-T units; IC550, pin
3) via the level converter (IC55).
74
PDATC
Outputs the data signal to the 1st and
2nd PLL ICs (MAIN-R/MAIN-T units;
IC400, pin 15, IC550, pin 5) via the
level converter (IC55).
75
PSCKC
Outputs clock signal to the 1st and
2nd PLL ICs (MAIN-R/MAIN-T units;
IC400, pin 14, IC550, pin 4) via the
level converter (IC55).
76
P1STC
Outputs strobe signal to the 1st PLL
ICs (MAIN-R/MAIN-T units; IC400, pin
16) via the level converter (IC55).
77
+5AC
Outputs control signal to the 5A
and D+5 regulator circuits (MAIN-R/
MAIN-T units; Q1345, Q1347) via the
level converter (IC55).
Low:
While the +5 and D+5 regu-
lators are activated.
85
PCON
Outputs control signal to the TX power
controller (MAIN-T unit; Q1250).
86
ULCK
Input port for the PLL unlock signal.
High: The PLL circuit is unlocked.
94
TXS
Outputs control signal to the T+5,
T+3 regulator circuits (MAIN-T unit;
Q1336, Q1342).
High:
During transmit.
95
RXS
Outputs control signal to the R+5,
R+3 regulator circuits (MAIN-R unit;
Q1337, Q1343).
High:
During receive.
103
AFCSW
Outputs control signal to AFC switch
(IC352, pin 5).
105
DACK2
Outputs clock signal to the D/A con-
verter (IC57, pin 7).
106
DADAT2
Outputs the data signal to the D/A
converter (IC57, pin 6).
107
DACK1
Outputs clock signal to the D/A con-
verter (IC56, pin 7).
4-4-2 MAIN-R/MAIN-T UNITS VOLTAGE LINE
Line
Description
HV
The voltage from a DC power supply.
VCC
The same voltage as the HV line which
is controlled by the power switching cir-
cuit (Q23, Q24). When the power switch is
pushed, the CPU outputs the "PWR" control
signal to the power switching circuit to turn
the circuit ON.
+9
Common 9 V converted from the HV line at
the +9 regulator circuit (IC1330). The output
voltage is applied to the 1st VCO (Q471),
etc.
+5
Common 5 V converted from the +9V line at
the 5 V regulator circuit (IC1331). The out-
put voltage is applied to the APC amplifier
(IC1251) and buffer amplifi er (Q710), etc.
DM+5
(MAIN-T unit
only)
Common 5 V converted from the +9V line at
the 5 V regulator circuit (IC830). The output
voltage is applied to the modulation ampli-
fi ers (IC831, IC832), etc.
T+9
(MAIN-T unit
only)
Transmit 9 V controlled by the T+9 regula-
tor circuit (Q1333, Q1334, D1331) using the
"TXS" signal from the CPU (LOGIC-T unit;
IC50, pin 94). The output voltage is applied
to the APC amplifi er (IC1250), etc.
T+5
(MAIN-T unit
only)
Transmit 5 V controlled by the T+5 regula-
tor circuit (Q1336, D1332, D1333) using the
"TXS" signal from the CPU (LOGIC-T unit;
IC50, pin 94). The output voltage is applied
to the RF amplifi er (IC1021), etc.
R+5
(MAIN-R unit
only)
Receive 5 V controlled by the R+5 regulator
circuit (Q1337) using the "RXS" signal from
the CPU (LOGIC-R unit; IC50, pin 95). The
output voltage is applied to the RF amplifi er
(Q2) and 1st mixer (IC71), etc.
T+3
(MAIN-T unit
only)
Transmit 3 V controlled by the T+3 regulator
circuit (Q1342) using the "TXS" signal from
the CPU (LOGIC-T unit; IC50, pin 94). The
output voltage is applied to the 1st mixer
(IC960), etc.
R+3
(MAIN-R unit
only)
Receive 3 V controlled by the R+3 regulator
circuit (Q1343) using the "RXS" signal from
the CPU (LOGIC-R unit; IC50, pin 95). The
output voltage is applied to the RF amplifi er
(Q1), etc.