4-2-4 1ST MIXER CIRCUIT (MAIN-T UNIT)
The fi ltered signal from the low-pass fi lter (L892, L893, C904
–C907) is applied to the 1st mixer circuit (IC960, pins 1, 6).
The applied signal is mixed with the 1st LO signal coming
from the 1st VCO circuit (Q471, Q472, D471) via the buffer
amplifi ers (Q473, Q710) to convert into the RF signal. The
RF signal from the 1st mixer circuit (IC960, pin 6) is passed
through the bandpass filter (FI961) and then amplified at
the RF amplifier (IC1021). The amplified signal is passed
through the bandpass filter (FI1020) to suppress spurious
components.
The fi ltered signal is applied to the pre-drive circuit.
4-2-5 DRIVE/POWER AMPLIFIER CIRCUITS
(MAIN-T UNIT)
The drive/power amplifier circuits amplify the RF signal to
the to the output level.
The filtered RF signal from the bandpass filter (FI1020) is
amplifi ed at the pre-drive (Q1080), drive (Q1081) and power
(IC1160) amplifi ers to obtain a stable 10 W of output power.
The power amplifi ed signal from the power amplifi er (IC1160,
pin 4) is passed through the SWR detector circuit (D1166,
D1170), low-pass fi lter which contains strip-line and C1198,
and then applied to the transmit antenna connector (CASE;
W5) via J1 (CHASSIS-T).
4-2-6 APC CIRCUIT (MAIN-T UNIT)
The APC circuit protects power amplifi er from a mismatched
output load and stabilizes the output power.
The SWR detector circuit (D1166, D1170) detects the for-
ward signals and refl ection signals, and converts it into DC
voltage. The output voltage is at a minimum level when the
antenna impedance is matched with 50
Ω
and is increased
when it is mismatched.
The detected voltage is applied to the APC amplifier
(IC1250, pins 3, 4) and is compared with the reference volt-
age which is supplied from the CPU (LOGIC-T unit; IC50, pin
85) as "PCON" signal.
When antenna impedance is mismatched, the detected volt-
age exceeds the power setting voltage. The output voltage
of the APC amplifiers (IC1250, IC1251) controls the bias
voltage of the power amplifi er (IC1160) to reduce the output
power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUITS (MAIN-R/MAIN-T UNITS)
The PLL circuit provides stable oscillation of the 1st LO fre-
quencies and 2nd LO frequency. The PLL output compares
the phase of the divided VCO frequency to the reference
frequency. The PLL output frequency is controlled by the di-
vided ratio (N-data) of a programmable divider.
4-3-2 1ST PLL CIRCUITS (MAIN-R/MAIN-T UNITS)
The 1st PLL circuit oscillates the 1st LO frequencies, and
the signals are applied to the 1st mixer circuit. The oscillated
signals from the 1st VCO circuit (Q471, Q472, D471) are
applied to the buffer amplifi ers (Q473, Q474) and are then
applied to the PLL IC (IC400, pin 6).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc.
The applied signal is divided at the prescaler and program-
mable counter section by the N-data ratio from the CPU
(LOGIC-R/LOGIC-T units; IC50). The divided signal is de-
tected on phase at the phase detector using the reference
frequency (X400: 15.3 MHz) and output from pin 4 (IC400).
The output signal is passed through the loop filter and is
then applied to the 1st VCO circuit.
The oscillated signal at the 1st VCO is buffer amplified at
Q473 and then passed through the bandpass fi lter (L474–
L477, C488–C497).
The filtered signal is applied to the buffer amplifier (Q710)
and then applied to the RX switch (MAIN-R unit; D711), and
TX switch (MAIN-T unit; D710).
E - 4 - 3
POWER
AMP.
APC
AMP.
APC
AMP.
DRIVE
AMP.
+
–
HV
to antenna
connector
PCON
RF signal
from 1st mixer
circuit
T+9
APC circuit
D1166
D1170
FOR
REV
Q1081
Q1080
IC1250
Q1250
IC1251
Q1082
IC1160
PER
DRIVE
• APC CIRCUITS