Icom id- rp2, Service Manual, Page: 104 / 150

E - 4 - 4
Loop
filter
X400
15.3 MHz
Q631, D630
2nd VCO
Buffer
Buffer
Buffer
Q771
Q632
IC551
Q633
IC550
Q400
to quadrature modulator
to 2nd mixer circuit
D771 MAIN-R unit only
MAIN-T unit only
MAIN-T unit only
MAIN-R unit only
D770
Mode
switch
LPF
PLL IC
Loop
filter
Q471, Q472,
D471
1st VCO
Buffer
Buffer
Buffer
Buffer
Q710
Q473
Q474
IC400
to 1st mixer circuit
to 1st mixer circuit
D711
D710
1ST PLL CIRCUIT
2ND PLL CIRCUIT
PLL IC
RECEIVE SIGNAL (MAIN-R UNIT)
The receive 1st LO signal from the RX switch (D711) is ap-
plied to the 1st mixer circuit (IC71).
TRANSMIT SIGNAL (MAIN-T UNIT)
The transmit signal from the TX switch (D710) is applied to
the 1st mixer circuit (IC960).
4-3-3 2ND PLL CIRCUIT (MAIN-R/MAIN-T UNITS)
The 2nd PLL circuit oscillates the 2nd LO frequency, and
the signal is applied to the 2nd mixer circuit and quadrature
modulator.
The signal oscillated at the 2nd VCO circuit (Q631, D630) is
amplifi ed at the buffer amplifi ers (Q632, Q633) via low-pass
filter (L631, C653, C654) and then applied to the PLL IC
(IC550, pin 19). The applied signal is divided at the prescaler
and programmable counter section by the N-data ratio from
the CPU (LOGIC-R/LOGIC-T units; IC50). The divided signal
is detected on phase at the phase detector using the refer-
ence frequency (X400: 15.3 MHz) and output from pin 13
(IC550).
The detected signal is passed through the loop fi lter (R555–
R557, C564, C567) and then applied to the 2nd VCO circuit.
The oscillated signal at the 2nd VCO is amplifi ed at the buffer
amplifi ers (Q632 Q771) and is then applied to the RX switch
(MAIN-R unit; D771), and TX switch (MAIN-T unit; D770).
RECEIVE SIGNAL (MAIN-R UNIT)
The receive 2nd LO signal from the RX switch (D771) is ap-
plied to the 2nd mixer circuit (Q131).
TRANSMIT SIGNAL (MAIN-T UNIT)
The transmit signal from the TX switch (D770) is applied to
the quadrature modulator (IC890).
• PLL CIRCUITS
4-4 POWER SUPPLY CIRCUITS
4-4-1 LOGIC-R/LOGIC-T UNITS VOLTAGE LINE
Line Description
5V
Common 5 V controlled by the +5 V regula-
tor circuit (IC500, Q500, Q501) using the
“PWRS” signal from the CPU (IC50, pin
101). The output voltage is applied to the
baseband filters (IC300–302), etc.
3.3V
Common 3.3 V converted from the 5V line
by the 3.3V regulator circuit (IC502). The output
voltage is applied to the FPGA IC (IC200) and
buffer amplifier (IC901), etc.
3.3V
Common 3.3 V converted from the 5V line
by the 3.3V regulator circuit (IC504). The output
voltage is applied to the CPU (IC50) and A/D
converter (IC55), etc.