IBM Power 595, Technical Overview And Introduction

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Chapter 2. Architectural and technical overview
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Figure 2-29 Power 595 processor book (shown in upper placement orientation)
Each MCM, shown in Figure 2-30, contains one dual-core POWER6 processor chip and two
L3 cache chips.
Figure 2-30 Multi-Chip Module (MCM)
The POWER6 processor chip provides 4 MB of on-board, private L2 cache per core. A total of
32 MB L3 cache is shared by the two cores.
2.6.1 POWER6 processor
The POWER6 processor capitalizes on all of the enhancements brought by the POWER5
processor. The POWER6 processor implemented in the Power 595 server includes additional
Note: All eight processor books are identical. They are simply inverted when plugged into
the bottom side of the mid-plane.
Memory DIMM Slots
(24x)
Node Controller
FSP1 Cards (2x)
Wide GX I/O Cards (2x)
MCMs (4x)
DCAs (2x)
Memory DIMM Slots
(8x)
Narrow GX I/O
Cards (2x)
Memory DIMM Slots
(24x)
Node Controller
FSP1 Cards (2x)
Wide GX I/O Cards (2x)
MCMs (4x)
DCAs (2x)
Memory DIMM Slots
(8x)
Narrow GX I/O
Cards (2x)
L3
L3
POWER6
L3
L3
POWER6
L3
L3
POWER6
L3
L3
POWER6