Appendix A. Connector Pin Assignments
IDE Connectors
1
2
40
39
Figure 36 (Page 3 of 3). System Memory Connector Pin Assignments
Pin
Signal
I/O
Pin
Signal
I/O
80
PD3
O
164
PD4
O
81
PD5
O
165
PD6
O
82
PD7
O
166
PD8
O
83
ID0
O
167
ID1
O
84
VDD
NA
168
VDD
NA
Figure 37. IDE Connector Pin Assignments
Pin
Signal
I/O
Pin
Signal
I/O
1
RESET
O
21
NC
NA
2
Ground
NA
22
Ground
NA
3
Data bus bit 7
I/O
23
IO Write
O
4
Data bus bit 8
I/O
24
Ground
NA
5
Data bus bit 6
I/O
25
IO Read
O
6
Data bus bit 9
I/O
26
Ground
NA
7
Data bus bit 5
I/O
27
IO Channel Ready
I
8
Data bus bit 10
I/O
28
ALE
O
9
Data bus bit 4
I/O
29
NC
NA
10
Data bus bit 11
I/O
30
Ground
NA
11
Data bus bit 3
I/O
31
IRQ
I
12
Data bus bit 12
I/O
32
CS16#
I
13
Data bus bit 2
I/O
33
SA1
O
14
Data bus bit 13
I/O
34
PDIAG#
I
15
Data bus bit 1
I/O
35
SA0
O
16
Data bus bit 14
I/O
36
SA2
O
17
Data bus bit 0
I/O
37
CS0#
O
18
Data bus bit 15
I/O
38
CS1
O
19
Ground
NA
39
Active#
I
20
Key (Reserved)
NA
40
Ground
NA
34
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