Appendix B. System Address Maps
Input/Output Address Map
The following figure lists resource assignments for the I/O address map. Any addresses that are not
shown are reserved.
Figure 50 (Page 1 of 3). I/O Address Map
Address (Hex)
Device
0000–001F
DMA 1
0020–002D
Interrupt controller 1
002E–002F
Plug and Play index registers
0030–003F
Interrupt controller 1
0040–0043
Timer 1
0044–0047
Available I/O for ISA/PCI bus
0048–0049
Power Management
004A–0053
Available I/O for ISA/PCI bus
0054–0057
GPIO CPU speed detect
0058–005B
GPIO PAP jumper, VPD, Flash/EEPROM lock, APC Power-off Request
005C–005D
Power Management
005E–005F
Available I/O for ISA/PCI bus
0060
Keyboard controller data byte
0061
System Port B
0062–0063
Available I/O for ISA/PCI bus
0064
Keyboard controller, command and status byte
0065–006F
Available I/O for ISA/PCI bus
0070, bit 7
Enable/disable NMI
0070, bits 6:0
Real time clock address
0071
Real time clock data
0072–0077
Available I/O for ISA/PCI bus
0078
GPIO CPU speed detect
0079
National 87307 GPIO
007A-007B
Available to ISA bus
007C
L2 Cache ID, SMI/PCI IRQ enable
007D
PCI interrupts to SMI enable
0080
POST Checkpoint register
0080-008F
DMA page register
0090–009F
Available I/O for ISA/PCI bus
00A0–00B1
Interrupt controller 2
00B2–00B3
Power management
00B4–00BF
Interrupt controller 2
00C0–00DF
DMA 2
00E0–00EF
Available I/O for ISA/PCI bus
00F0
Coprocessor busy–Clear
00F1–00FF
Available I/O for ISA/PCI bus
0100–016F
Available I/O for ISA/PCI bus
0170–0177
IDE channel 1
Appendix B. System Address Maps
45
