Appendix A. Connector Pin Assignments
System Memory Connector
1
85
84
168
Figure 36 (Page 1 of 3). System Memory Connector Pin Assignments
Pin
Signal
I/O
Pin
Signal
I/O
1
GND
NA
85
GND
NA
2
MD0
I/O
86
MD32
I/O
3
MD1
I/O
87
MD33
I/O
4
MD2
I/O
88
MD34
I/O
5
MD3
I/O
89
MD35
I/O
6
VDD
I/O
90
VDD
NA
7
MD4
I/O
91
MD36
NA
8
MD5
I/O
92
MD37
I/O
9
MD6
I/O
93
MD38
I/O
10
MD7
I/O
94
MD39
I/O
11
PAR0
I/O
95
PAR4
I/O
12
GND
NA
96
GND
NA
13
MD16
I/O
97
MD48
I/O
14
MD17
I/O
98
MD49
I/O
15
MD18
I/O
99
MD50
I/O
16
MD19
I/O
100
MD51
I/O
17
MD20
I/O
101
MD52
I/O
18
VDD
NA
102
VDD
NA
19
MD21
I/O
103
MD53
I/O
20
MD22
I/O
104
MD54
I/O
21
MD23
I/O
105
MD55
I/O
22
PAR2
I/O
106
PAR6
I/O
23
GND
I/O
107
GND
NA
24
NC
NA
108
NC
NA
25
NC
NA
109
NC
NA
26
VDD
NA
110
VDD
NA
27
WE0
I
111
NC
NA
28
CAS0
I
112
CAS2
I
29
CAS2
I
113
CAS3
I
30
RAS0
I
114
RAS1
I
31
OE0
I
115
NC
NA
32
GND
NA
116
GND
NA
33
A0A
I
117
A1
I
34
A2
I
118
A3
I
35
A4
I
119
A5
I
36
A6
I
120
A7
I
32
Technical Information Manual