IBM p5 590, System Handbook

Page: 63 / 316

Chapter 2. Hardware architecture
41
Figure 2-11 Single loop 7040-61D
2.7.4 Half-drawer cabling
Although I/O drawers will not be built in half-drawer configurations, they can be
cabled to, and addressed by the CEC, in half drawer increments (Figure 2-12).
Both STI connectors on one CEC I/O card Px-Cx-T1 and Px-Cx-T2 will be cabled
to both ports on P1 RIO-2 Riser card.
Both STI connectors on a different CEC I/O card Px-Cx-T1 and Px-Cx-T2
(possibly on a different processor book) will be cabled to both ports on P2 RIO-2
Riser card.
CP B
CP A
1
RIO-2
CARD
0
1
RIO-2
CARD
0
1
0
1
0
RIO-2
CARD
RIO-2
CARD
P1 P2
P1 P2
0 1
0
1
CEC GX+ I/O
RIO-2 PORTS