IBM p5 590, System Handbook

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Chapter 2. Hardware architecture
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associated L3 cache and memory are packaged on a single processor book.
Access to memory behind another processor is accomplished through the fabric
buses. The p5-590 supports up to two processor books (each book is a 16-way)
and the p5-595 supports up to four processor books. Each processor book has
dual MCMs containing POWER5 processor chips and 36 MB L3 modules. Each
16-way processor book also includes 16 slots for memory cards and six remote
I/O-2 (RIO-2) attachment cards for connection of the system I/O drawers as
shown in Figure 2-3.
Figure 2-3 p5-590 and p5-595 16-way processor book diagram
2.2.6 Processor clock rate
The p5-590 system features base 8-way (CoD), 16-way, and 32-way
configurations with the POWER5 processor running at 1.65 GHz. The p5-595
system features base 16-way, 32-way, 48-way, and 64-way configurations with
the POWER5 processor running at 1.65 GHz and 1.9 GHz.
To determine the processor characteristics on a running system, use one of the
following commands:
lsattr -El proc X Where X is the number of the processor; for example,
proc0 is the first processor in the system. The output from
the command
3
would be similar to this:
Note: Any p5-595 or p5-590 system made of more than one processor book
must have all processor cards running at the same speed.