IBM 8687 - Eserver xSeries 440, Planning And Installation Manual

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xSeries 440 Planning and Installation Guide
x440s with Xeon DP processors are a good platform for customers who are
looking for better price/performance platforms but still maintain high levels of
scalability that the x440 provides.
Lab tests using standard transaction processing benchmark conditions have
shown that the comparative performance of the Xeon DP and Xeon MP x440s is
approximately the following:
򐂰 Two-way 1.6 GHz Xeon MP (1 MB L3 cache) = 1.0
򐂰 Two-way 2.4 GHz Xeon DP (0 MB L3 cache) = 1.10
򐂰 Four-way 1.6 GHz Xeon MP (1 MB L3 cache) = 1.70
򐂰 Four-way 2.4 GHz Xeon DP (0 MB L3 cache) = 1.65
2.2.3 XceL4 Server Accelerator Cache
The XceL4 Server Accelerator Cache (L4 cache) is 32 MB of PC200-compliant
DDR-SDRAM using a 64-bit 400 MHz bus with 3.2 GBps throughput.
32MB of L4 high-performance high-speed ECC cache memory per four-way
SMP Expansion Module speeds up your most complex applications by reducing
memory latency and increasing memory bandwidth. The more high-speed cache
memory there is, the more often the processor finds the data it needs and the
less often it has to access main memory.
XceL4 server Accelerator cache provides the following benefits:
򐂰 XceL4 server Accelerator Cache delivers up to 20% more performance for
transaction-intensive workloads.
򐂰 Minimizes processor and I/O memory contention delivering full PCI-X
bandwidth to network and storage devices.
򐂰
Advanced Level 4 caching is designed to provide zero wait-state memory
access, up to 3X performance increase over typical main memory fetches.
2.2.4 High-performance memory subsystem
The x440 memory subsystem provides multiple levels of redundancy, combining
memory mirroring, Chipkill, Memory ProteXion, and memory scrubbing.
Combining Chipkill with Memory ProteXion means that up to two failed memory
chips (“chipkills”) per memory port on an x440 can be tolerated. A 16-way x440
with its eight memory ports could sustain up to 16 failed chips.
The first chipkill on each port would not even generate a Light Path error,
because Memory ProteXion would provide the first layer of protection. Each
memory port could then sustain a second chipkill without shutting down.
Provided that Active Memory with memory mirroring is enabled, the third chipkill