IBASE Technology ET976, Design Manual

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COM Express® Carrier Board Design Guide 9
Signal Pin# Description I/O Remarks
P
PEG_RX12- C91
C92 PEG channel 12, Receive
Input differential pair. I PCIE
P
PEG_TX12- D91
D92 PEG channel 12, Transmit
Output differential pair. O PCIE
P
PEG_RX13- C94
C95 PEG channel 13, Receive
Input differential pair. I PCIE
P
PEG_TX13- D94
D95 PEG channel 13 Transmit
Output differential pair. O PCIE
P
PEG_RX14- C98
C99 PEG channel 14, Receive
Input differential pair. I PCIE
P
PEG_TX14- D98
D99 PEG channel 14, Transmit
Output differential pair. O PCIE
P
PEG_RX15- C101
C102 PEG channel 15, Receive
Input differential pair. I PCIE
P
PEG_TX15- D101
D102 PEG channel 15, Transmit
Output differential pair. O PCIE
SDVO_I2C_CLK D73 I2C based control signal
(clock) for SDVO device. O 2.5V
CMOS SDVO enabled if this line is pulled up to
2.5V on Carrier or on ADD2 (Type 2 only)
SDVO_I2C_DATA C73 I2C based control signal
(data) for SDVO device I/O 2.5V
OD CMOS SDVO enabled if this line is pulled up to
2.5V on Carrier or on ADD2 (Type 2 only)
PEG_LANE_RV# D54 PCI Express Graphics lane
reversal input strap. Pull
low on the carrier board to
reverse lane order. I 3.3V
CMOS
PEG_ENABLE# D97 PEG enable function.
Strap to enable PCI
Express x16 external
graphics interface. Pull
low to disable internal
graphics and enable the
x16 interface. I 3.3V
CMOS Type 2 only
PCIE_
PCIE_CLK_REF- A88
A89 PCIe Reference Clock for
all COM Express PCIe
lanes, and for PEG lanes O CMOS COM Express only allocates a
single reference clock