I-Bus IBC 2600, User Manual

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Chapter 4 - Advanced Setup
4-15 IBC 2600 User’s Guide
Available options are:
Disabled
Enabled
DRAM Integrity Mode
This option allows you to set the type of system memory checking used
in your system.
The Setup screen displays the system option:
DRAM Integrity Mode None
Three options are available:
S
None - No error checking or error reporting is done.
S
EC - Multibit errors are detected and reported as parity errors.
Single-bit errors are corrected by the chipset. Corrected bits of
data from memory are not written back to DRAM system
memory.
S
ECC Hardware - Multibit errors are detected and reported as
parity errors. Single-bit errors are corrected by the chipset and
are written back to DRAM system memory.
If a soft (correctable) memory error occurs, writing the fixed data
back to DRAM system memory will resolve the problem. Most
DRAM errors are soft errors. If a hard (uncorrectable) error
occurs, writing the fixed data back to DRAM system memory
does not solve the problem. In this case, the second time the
error occurs in the same location, a Parity Error is reported,
indicating an uncorrectable error.
DRAM Refresh Rate
This option specifies the interval between refresh signals to DRAM sys-
tem memory. Settings are in microseconds (”
←
s”).
The Setup screen displays the system option:
DRAM Refresh Rate 15.6
←
s