I-Bus 0818D, User Manual

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Appendix 1 – Technical Reference
0818D User’s Guide A1-7
P2 Signal Descriptions
General V(I/O) 5V or 3.3V power
GND To digital ground plane
PCI Bus Signals AD(32:63) Address/Data bus
(64-bit extension) C/BE(4:7)_ Command/Byte Enable bus
PAR64 64-bit Bus parity
BRSVPxxx PCI bus reserved signals
PCI bus arbitration GNT(6:1)_ Bus grants
signals REQ(6:1)_ Bus requests
PCI bus clocks CLK(6:1)
Miscellaneous signals PRST_ Push Button Reset
DEG_ Degrade signal (Power Supply)
FAL_ Supply Fail Signal
(Power Supply)
GA(4:0) Geographic Addressing
SYSEN_ System slot identification
(Grounded at the system slot)
64EN_ 64-bit bus enable
P3, P4, P5 Connectors Pin Assignments (System Slot)
P3, P4, and P5 are used for the purpose of providing access to the
rear I/O. There is no connection on the backplane to these
connectors at the system slot. The P3, P4, and P5 connector pinouts
are unique to the CP1500 Sparc CPU board and described in the
SPARCengine CP1500 360MHz/440MHz Technical Reference and
Manual, located at the Sparc web site:
http://www.sun.com/microelectronics/SPARCengineCP/1500