Hynix Semiconductor HMS81004E, User Manual

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HMS8132E/HMS81032TL
Nov. 2001 Ver 2.00 39
Figure 13-1 Block Diagram of Timer/Counter
T0HMD T0HLD T0LMD T0LLD
T1HD T1LD T2DR
Timer0 (16bit)
Polarity
Timer2(8bit)
Timer1(8bit)
Selection
Edge
Selection
Tout
Logic
BTC L - T O U T1 TO U T0 T0O U TP TO U TS TO U TB
T0IN IT T1IN IT
7 0
TM01
from
EC/R14
from
INT2/R12
(Capture Signal)
T0OUT
(R17)
TOUT
(REMOUT)
T1OUT
(R16)
T2OUT
(R15)
BT C L
7 6 5 4 3 2 1 0
-
INITIAL VALUE: 00
H
ADDRESS: 0DA
H
TM01
T O U T 1 T O U T 0
R/W R/W R/W R/W R/W
T0O U TP
Timer 01 mode register
TOUT LOGIC
0: Timer1 output low
1: Timer1 output high
Timer1 output initial value
0: T0OUT Polarity Equal to TOUT Logic input signal
1: T0OUT Polarity Reverse to TOUT Logic input signal
T0OUT Polarity Selection
(TOUT Logic or TOUTB)
0: Bit(TOUTB) Output Through REMOUT
REMOUT Port Output Selection
0: REMOUT Output Low
1: REMOUT Output High
REMOUT Port Bit Control
R/W R/W
TO U TS T O U T B
00: AND of T0 OUTPUT and T1 OUTPUT
01: NAND of T0 OUTPUT and T1 OUTPUT
10: OR of T0 OUTPUT and T1 OUTPUT
11: NOR of T0 OUTPUT and T1 OUTPUT
T 0IN IT T 1IN IT
1: TOUT Logic Output Through REMOUT
0: Timer0 output low
1: Timer0 output high
Timer0 output initial value