Hynix Semiconductor HMS81004E, User Manual

Page: 52 / 94

HMS81032E/HMS81032TL
48 Nov. 2001 Ver 2.00
14.3 Interrupt accept mode
The interrupt priority order is determined by bit (IM1,
IM0) of IMOD register. The condition allow for accepting
interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be “1”. In Reset state, these
IP3 - IP0 registers become all “0”.
.
Figure 14-2 Interrupt Enable & Request Flag
0: Disable
1: Enable
VALUE
R/W
INITIAL VALUE: 000- 000-
B
ADDRESS: 0CE
H
IENH INT1E
MSB LSB
T0E T1E INT2E
R/W
External interrupt 1
INITIAL VALUE: -00- ----
B
ADDRESS: 0CC
H
IENL
MSB LSB
Timer1
R/W R/W R/W R/W
Basic Interval Timer Watchdog timer
External interrupt 2
Key scan
WDTE
R/W R/W
- - - - - BITE
-
- -
KSCNE T2E
Timer2
Timer0
R/W
INITIAL VALUE: 000- 000-
B
ADDRESS: 0CF
H
IRQH INT1R
MSB LSB
T0R T1R INT2R
R/W
External interrupt 1
INITIAL VALUE: -00- ----
B
ADDRESS: 0CD
H
IRQL
MSB LSB
Timer1
R/W R/W R/W R/W
Basic Interval Timer Watchdog timer
External interrupt 2
Key scan
WDTR
R/W R/W
- - - - - BITR
-
- - KSCNR T2R
Timer2
Timer0