GMS81C5108
72
JUNE 2001 Ver 1.0
19.2 Control of LCD Driver Circuit
The LCD driver is controlled by the LCD Control Register
(LCR). The LCR[1:0] determines the frequency of COM
signal scanning of each segment output. RESET clears the
LCD control register LCR values to logic zero. The LCD
display can continue to operate during SLEEP and STOP
modes if a sub-frequency clock is used as system clock
source. The constant voltage booster circuit for using LCD
driver is built in, so the definite voltage could supplied re-
gardless of power source voltage fluctuations.
Note: The Sub clock is used as voltage booster source
clock, so the stabilization time is need to use voltage boost-
er. Normally, the stabilization time is need more than
500ms. The external bias registers cannot be used for LCD
display supply voltage.
Figure 19-2 LCD Control Register
Selecting Frame Frequency
Frame frequency is set to the base frequency as shown in
the following Table 19-1. The f
S
is selected to f
SUB
(sub
clock) which is 32.768kHz.
The matters to be attended to use LCD driver
In reset state, LCD source clock is sub clock. So, when the
power is supplied, the LCD display would be flickered be-
fore the oscillation of sub clock is stabilized. It is recom-
mended to use LCD display on after the stabilization time
of sub clock is considered enough. If the LCD is reset dur-
ing display, the display would be blotted by the capacity of
LCD power circuit. The external circuit of constant voltage
booster for using LCD driver is shown at right.
Figure 19-3 LCD Power Booster Circuit
LCDEN (LCD Display Enable Bit)
0: LCD Display Disable
1: LCD Display Enable
VBCL (Voltage Booster Enable Bit)
0: Voltage Booster Disable
1: Voltage Booster Enable
LCDD[1:0] (LCD Duty Selection)
00: 1/4 Duty
01: 1/3 Duty (COM[3] are used as SEG[34])
LCR(LCD Control Register)
ADDRESS : 0F1
H
RESET VALUE : --000000
B
-
-
LCDEN
VBCL
LCDD1
LCDD0
LCK1
LCK0
Bit : 7 6 5 4 3 2 1 0
R/W
R/W
R/W
R/W
R/W
R/W
LCK (LCD Clock source selection)
00: f
S
÷
32
01: f
S
÷
64
10: f
S
÷
128
11: f
S
÷
256
*
The fs can be selected among f
SUB
(Sub clock), f
MAIN
÷
2
7
(Main clck) and f
MAIN
(Main clock).
10: 1/2 Duty (COM[3:2] are used as SEG[34:35])
11: Static (COM[3:1] are used as SEG[34:36])
And sub or main is selected by WTCK[1:0] of WTMR.
LCR[1:0]
LCD clock
Frame Frequency (Hz)
Duty = Static
Duty = 1/2
Duty = 1/3
Duty = 1/4
00
01
10
11
f
S
÷
32
f
S
÷
64
f
S
÷
128
f
S
÷
256
1024
512
256
128
512
256
128
64
341.3
170.7
85.3
42.7
256
128
64
32
Table 19-1 Setting of LCD Frame Frequency
VCL2
VCL1
VCL0
R1
R2
C1
GMS81C5108
GMS87C5108
C2
C3
C4
CAPH
CAPL
C1~C4=0.47uF
R1=400K
Ω
R2=1M
Ω
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