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GMS81C5108
34
JUNE 2001 Ver 1.0
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. Power consumption can
be reduced by switching them to the low power operation
frequency clock can be easily obtained by attaching a res-
onator between the X
IN
and X
OUT
pin and the SX
IN
and
SX
OUT
pin, respectively. The system clock can also be ob-
tained from the external oscillator.
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware. The internal system clock can be selected
by bit2, and bit3 of the system clock mode register (SC-
MR). The registers are shown in Figure 10-2.
To the peripheral block, the clock among the not-divided
original clocks, divided by
2
, 4,...,
up to 1024 can be pro-
vided. Peripheral clock is enabled or disabled by STOP in-
struction. The peripheral clock is controlled by clock
control register (CKCTLR). See "11. BASIC INTERVAL
TIMER" on page 43 for details.
Figure 10-1 Block Diagram of Clock Generator
CPU clock
Instruction cycle time
f
MAIN
= 4MHz
f
SUB
= 32.768kHz
÷
2
0.5 us
61 us
÷
8
2.0 us
244 us
÷
16
4.0 us
488 us
÷
64
16.0 us
1953 us
Internal system clock
SX
IN
PRESCALER
0
1
X
IN
÷
1
Peripheral clock
MUX
÷
2
÷
4
÷
8
÷
16
÷
128
÷
256
÷
512
÷
1024
÷
32
÷
64
÷
2
÷
8
÷
16
÷
64
select clock
SCS[1:0]
OSC Stop
SYCC<1>
SYCC<0>
STOP Mode
SLEEP Mode
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
** Clock is frozen by STOP or SLEEP[SMR.0] Instruction.
** Clock is released
1) by BIT overflow when previos state has been STOP mode.
2) by interrupts when previos state has been SLEEP mode.
PRES
CAL
E
R
f
EX
(Hz)
PS0
PS3
PS2
PS4
PS1
PS10
PS9
PS5
PS6
PS7
4M
Frequency
period
4M
1M
500K
250K
2M
125K
62.5K
250n
500n
1u
2u
4u
8u
16u
32u
64u
256u
128u
3.906K
7.183K
15.63K
31.25K
PS8
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