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Hynix Semiconductor GMS81C5108, User Manual

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Hynix Semiconductor GMS81C5108 User Manual Download Page 57

GMS81C5108

54

JUNE 2001   Ver 1.0

less PWM output. In Figure 12-11, the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle).

The bit POL0 of TM1 decides the polarity of duty cycle.

The duty value can be changed when the PWM outputs.
However the changed duty value is output after the current
period is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-13. As it were, the absolute duty time is not
changed in varying frequency. 

Note: If the user need to change mode from the Timer1

mode to the PWM mode, the Timer1 should be
stopped firstly, and then set period and duty register
value. If user writes register values and changes
mode to PWM mode while Timer1 is in operation,
the PWM data would be different from expected
data in the beginning.

The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.

PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock

PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock

If it needed more higher frequency of PWM, it should be
reduced resolution.

Note: If the duty value and the period value are same, the

PWM output is determined by the bit POL0 (1: High,
0: Low). And if the duty value is set to “00

H

”

, the

PWM output is determined by the bit POL0(1: Low,
0: High). The period value must be same or more
than the duty value, and 00

H 

cannot be used as the

period value.

Table 12-2 PWM Frequency vs. Resolution at 4MHz

Figure 12-11 PWM Mode

Resolution

Frequency

T1CK[1:0]

=00 (250nS)

T1CK[1:0]

=01 (500nS)

T1CK[1:0]

=10 (2uS)

10-bit

3.9KHz

1.95KHz

0.49KHZ

9-bit

7.8KHz

3.9KHz

0.98KHZ

8-bit

15.6KHz

7.8KHz

1.95KHz

7-bit

31.25KHz

15.6KHz

3.90KHz

÷

 1

÷

 2

÷

 8

PWMHR

ADDRESS : 0E5

H

RESET VALUE : ----0000

B

-

-

-

-

PWM03

PWM02

PWM01

PWM00

X

X

X

X

MUX

1

T1CN

T1CK[1:0]

T1 (8-bit)

T1ST

0 : Stop
1 : Clear and Start

CLEAR

COMPARATOR

COMPARATOR

T1PDR (8-bit)

PWMHR[1:0]

T1PPR (8-bit)

PWMHR[3:2]

T1PDR (8-bit)

S

Q

R

POL

PWMO

R31/PWM

T0 clock source

TM1

ADDRESS : 0E2

H

RESET VALUE : 00

H

POL

16BIT

PWME

CAP1

T1CK1

T1CK0

T1CN

T1ST

X

0

1

0

X

X

X

X

[PMR.6]

Period High

Duty High

Slave

Master

Bit Manipulation Not Available

X : The value “0” or “1” corresponding your operation.

SX

IN

0X

1X

X

IN

SCMR[1:0]

2

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Summary of Contents for GMS81C5108

Page 1: ...HYNIX SEMICONDUCTOR INC 8 BIT SINGLE CHIP MICROCONTROLLERS GMS81C5108 User s Manual Ver 1 0 Downloaded from Elcodis com electronic components distributor...

Page 2: ...tives listed at address directory Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice The information diagrams and other data in this manual ar...

Page 3: ...ode 50 8 Bit Capture Mode 50 16 bit Capture Mode 53 8 Bit 16 Bit Compare OutPut Mode 53 PWM Mode 53 13 Watch Timer Watch Dog Timer 56 Watch Timer 56 Watch Dog Timer 57 14 Analog To Digital Converter 5...

Page 4: ...ay RAM Instruction Cycle Time 1us at 4MHz 2 cycle NOP instruction 24 Programmable I O pins 2V to 4V Operating Range Dual Clock Operation main 400kHz 4 2MHz sub 32 768kHz One 8 bit Basic Interval Timer...

Page 5: ...erent type programmers such as single type and gang type For mode detail refer to OTP Programming chapter Macro assembler operates under the MS Windows 95 98TM Please contact sales part of Hynix Semic...

Page 6: ...SXIN SXOUT Segment Drive Output SEG0 SEG33 Common Drive Output COM0 R00 INT0 R01 INT1 R02 INT2 R03 EC0 R04 BUZ R05 SCK R06 SO R07 SI R10 KS0 R11 KS1 R12 KS2 R13 KS3 R14 KS4 R15 KS5 R16 KS6 R17 KS7 R30...

Page 7: ...8 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 X OUT X IN V DD REMOUT R07 SI R06 S0 R05 SCK R04 BUZ R03 EC0 R02 INT2 R01 INT1 R33 R32 R31 PWM R30 R17 KS7 R16 KS6 R15 KS5 R14 KS4 R13 KS3 R12 KS...

Page 8: ...M Figure 4 1 Package Diagram 20 10 19 90 24 15 23 65 18 15 17 65 14 10 13 90 3 10 max 0 45 0 30 0 8 BSC SEE DETAIL A 1 03 0 73 0 7 0 36 0 10 0 23 0 13 1 95 REF DETAIL A UNIT mm max min Downloaded from...

Page 9: ...software In addition R1 serves the functions of the various follow ing special features R20 R23 R2 is a 4 bit CMOS bidirectional I O port Each pins 1 or 0 written to the Port Direction Register can be...

Page 10: ...CAPH CAPL 74 75 LCD drive voltage booster capacitor Internal VCL0 Connected State of before STOP SEG0 SEG33 34 32 1 O LCD segment output Segment output COM0 76 O LCD common output Common output SEG34...

Page 11: ...Pull up Tr Open Drain Reg BUZ SO RD Data Bus Pin Data Reg Dir Reg Pull up Reg MUX RD VDD VSS Pull up Tr Open Drain Reg SCK OUT Noise Canceller SCK IN RD Data Bus SCK IN _EN Pin Data Reg Dir Reg Pull...

Page 12: ...us Pin Data Reg Dir Reg Pull up Reg MUX RD VDD VSS Pull up Tr Open Drain Reg PWMO RD Data Bus Pin LCD Data DB VCL2 or VCL1 VCL1 or VSS LCD Control Reg Frame Counter VCL2 Pin VCL2 or VCL1 VCL1 or VSS L...

Page 13: ...TP Internal RESET RESET VDD VSS Noise Canceller VDD Mask Option Default no pull up Internal RESET GMS81C5108 MASK Pin WDTOUT WDTOUTEN STOP XOUT XIN VDD VSS VDD VSS VDD Main frequency clock XOUT XIN VD...

Page 14: ...damage to the de vice This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implie...

Page 15: ...R3 VIN 0V 1 Output High Leakage Current IOH REMOUT VDD 3V VOH VDD 1 0V 30 5 mA Output Low Leakage Current IOL REMOUT VDD 3V VOL 1 0V 0 5 3 Pull up Resister RP1 R0 R3 VDD 3V 50 100 200 k RP2 RESET VDD...

Page 16: ...47uF 2 85VCL0 3 0VCL0 LCD Common Output Current ICOM Output Voltage Deviation 0 2V 30 A LCD Segment Output Current ISEG Output Voltage Deviation 0 2V 5 Parameter Symbol Condition Specifications Unit M...

Page 17: ...n Oscillation Stabilization Time 910kHz 60 Main Oscillation Stabilization Time 455kHz 100 Sub Oscillation Stabilization Time tSST SXIN SXOUT 1 2 S External Clock H or L Pulse Width tMCPW XIN 80 nS tSC...

Page 18: ...nput Clock H or L Pulse Width tSCKW tSYS 70 SCK Output Clock Cycle Time tSCYC 4tSYS 16tSYS SCK output Clock H or L Pulse Width tSCKW 2tSYS 30 SCK output Clock Delay Time tDS 100 SI input Setup Time Ex...

Page 19: ...epresents mean 3 and mean 3 respectively where is standard deviation IOL VOL VDD 4 2V mA IOL 1 0 3 0 2 0 VOL V IOH VOH VDD 4 2V 8 6 4 2 0 mA IOH 1 0 2 0 VOH V 70 C R0 R1 R2 R3 pin R Ta 200 100 0 k 25...

Page 20: ...e Main opr 6 4 2 1 0 MHz fMAIN 2 2 5 3 3 5 4 5 VDD V Operating Area ISTOP IDD3 VDD 4 3 2 1 0 A IDD 2 2 5 3 3 5 4 VDD V Stop Mode IDD4 VDD 100 75 50 25 0 A IDD 2 2 5 3 3 5 4 VDD V Normal Mode Sub opr I...

Page 21: ...lly SP is automatically updated when a subroutine call is executed or an interrupt is accepted However if it is used in excess of the stack area permitted by the data memory allocating configuration t...

Page 22: ...g mode In the direct addressing mode addressing area is from zero page 00H to 0FFH when this flag is 0 If it is set to 1 addressing area is assigned by RPR register address 0F3H It is set by SETG inst...

Page 23: ...At execution of RET instruction PCL PCH 00BF 00BF 00BE 00BD 00BC 00BD Pop up At execution of RETI instruction PCL PCH 00BF 00BF 00BE 00BD 00BC 00BC Pop up PSW 0000H 00BFH Stack depth At execution of...

Page 24: ...location where it commences the execution of the service routine The External interrupt 0 for example is assigned to loca tion 0FFFAH The interrupt service locations spaces 2 byte interval 0FFF8H and...

Page 25: ...ware interrupt is using same address with TCALL0 NOTE TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 BRK C9 CA CB...

Page 26: ...INT0 Int 0 DW BIT_INT BIT DW KEY_INT Key Scan DW RESET Reset ORG 0F000H MAIN PROGRAM RESET DI Disable All Interrupts CLRG LDX 0 RAM_CLR LDA 0 RAM Clear 0000H 00BFH STA X CMPX 0C0H BNE RAM_CLR LDX 0BFH...

Page 27: ...in each peripheral section Note Write only registers can not be accessed by bit ma nipulation instruction Do not use read modify write instruc tion Use byte manipulation instruction Example To write a...

Page 28: ...selection register IESR R W 0 0 0 0 0 0 byte bit 69 00D9 Port selection register PMR R W 0 0 0 0 0 0 byte bit 32 00DA Interrupt enable low register IENL R W 0 0 0 0 byte bit 65 00DB Interrupt enable...

Page 29: ...DHR W 1 1 1 1 1 1 1 1 byte 76 00FA Remocon data low register RDLR W 1 1 1 1 1 1 1 1 byte 76 Remocon data counter RDC R 0 0 0 0 0 0 0 0 byte bit 76 00FB Remocon output data register RODR R W 0 byte bit...

Page 30: ...e G 1 RPR 01H E45535 LDM 35H 55H 3 Direct Page Addressing dp In this mode a address is specified within direct page Example G 0 C535 LDA 35H A RAM 35H 4 Absolute Addressing abs Absolute addressing set...

Page 31: ...mode a address is specified within direct page by the X register and the content of X is increased by 1 LDA STA Example G 0 X 35H DB LDA X X indexed direct page 8 bit offset dp X This address value i...

Page 32: ...Assigns data address to use for accomplishing command which sets memory data or pair memory by Operand Also index can be used with Index register X Y JMP CALL Example G 0 3F35 JMP 35H X indexed indire...

Page 33: ...ND CMP EOR LDA OR SBC STA Example G 0 Y 10H 1725 ADC 25H Y Absolute indirect abs The program jumps to address specified by 16 bit absolute address JMP Example G 0 1F25E0 JMP 0E025H 05 25H 0E005H Y 10...

Page 34: ...by reset function On the other hand its in itial status is input Figure 9 1 Example of port I O assignment Pull up Control Registers The R0 R1 R2 and R3 ports have internal pull up resis tors Figure 9...

Page 35: ...ESS 0C0H RESET VALUE 00H R07 R06 R05 R04 R03 R02 R01 R00 Port Direction R0 Direction Register R0DR ADDRESS 0C8H RESET VALUE 00H 0 Input 1 Output Pull up select R0 Pull up R0PU ADDRESS 0D0H RESET VALUE...

Page 36: ...ut put through the R3DR register address 0CBH SEG0 SEG36 Segment signal output pins for the LCD display See 19 LCD DRIVER on page 71 for details COM0 COM3 Common signal output pins for the LCD display...

Page 37: ...clock among the not divided original clocks divided by 2 4 up to 1024 can be pro vided Peripheral clock is enabled or disabled by STOP in struction The peripheral clock is controlled by clock control...

Page 38: ...b clock on main clock on 11 sub clock on main clock off SCS 1 0 System clock source select 00 fMAIN 2 01 fMAIN 8 INITIAL VALUE 00H ADDRESS 0F5H SCMR System Clock Mode Register 10 fMAIN 16 11 fMAIN 64...

Page 39: ...this mode the CPU clock stops while peripherals and the oscillation source continue to operate normally STOP mode In this mode the system operations are all stopped holding the internal states valid i...

Page 40: ...low which immediately performs the reset operation After reset the GMS81C5108 is placed in Main active mode Example LDM SCMR 02H Turn on main clock CALL DELAY Wait until stable LDM SCMR 0 Move to mai...

Page 41: ...MR XXXX XX10B Operation clock Main clock operation Stabilizing Time 60ms Sub freq clock Main freq clock XIN pin SXIN pin Changed to the Transition Changed to the Main clock SCMR XXXX XX10B SCMR XXXX X...

Page 42: ...address 0DEH It is released by RESET or interrupt To be released by in terrupt interrupt should be enabled before Sleep mode Figure 10 5 SLEEP Mode Register Figure 10 6 Sleep Mode Release Timing by Ex...

Page 43: ...and must be held active long enough to allow the oscillator to restart and stabilize And after STOP instruction at least two or more NOP in struction should be written as shown in example below Periph...

Page 44: ...nd Control registers to retain their values Start up is performed to acquire the time for stabilizing os cillation During the start up the internal operations are all stopped Figure 10 8 STOP Mode Rel...

Page 45: ...ip with external circuit In input mode the pin impedance viewing from external MCU is very high that the current doesn t flow But input voltage level should be VSS or VDD Be careful that if unspecifie...

Page 46: ...fter one machine cycle by hard ware BITR and CKCTLR are located at same address and ad dress 0F4H is read as a BITR and written to CKCTLR Figure 11 1 Block Diagram of Basic Interval Timer Table 11 1 B...

Page 47: ...210 Clear bit 0 Normal operation free run 1 Clear 8 bit counter BITR to 0 This bit becomes 0 automatically INITIAL VALUE 0111B ADDRESS 0F4H after one machine cycle CKCTLR 7 6 5 4 3 2 1 0 INITIAL VALUE...

Page 48: ...ister is increased in response external interrupt same with timer function When external interrupt edge input the count register is captured into capture data register CDRx Timer1 is shared with PWM f...

Page 49: ...tart count again INITIAL VALUE 00000000B ADDRESS 0E2H TM1 Timer1 Mode Register R W R W R W R W T1CN T1ST T1CK1 T1CK0 R W R W POL PWM Output Polarity Selection 0 Duty Active Low 1 Duty Active High POL...

Page 50: ...e value of Timer 1 counter and in Capture mode this register is the value of input capture CDR17 CDR16 R R TDR1 Timer 1 Data Register TDR14 Bit 7 6 5 4 3 2 1 0 TDR15 INITIAL VALUE FFH ADDRESS 0E3H W W...

Page 51: ...Compare Output 0 0 0 1 XXX XX 1 8 Bit Timer Counter 10 Bit PWM 1 0 0 0 XXX 11 0 16 Bit Timer 1 0 0 0 111 11 0 16 Bit Event Counter 1 1 X1 0 XXX 11 0 16 Bit Capture 1 0 0 0 XXX 11 1 16 Bit Compare Out...

Page 52: ...s increased every 0 to 1 rising edge transition of EC0 pin In order to use counter function the bit R03 of the R0 Direction Register R0DR should be set to 0 and the bit EC0 of Port Mode Register PMR s...

Page 53: ...e captured value 13H is more little than wanted value It can be ob tained correct value by counting the number of timer over flow occurrence Timer Counter still does the above but with the added fea t...

Page 54: ...8 512 8 32 EC0 Edge Detector MUX MUX 1 1 T0 8 bit CDR0 8 bit T0IF CLEAR COMPARATOR TIMER 0 INTERRUPT T0ST 0 Stop 1 Clear and Start T0CN T1CN T0CK 2 0 T1CK 1 0 TDR0 8 bit INT0IF INT 0 INTERRUPT INT0 T1...

Page 55: ...u n t 0 1 2 3 4 5 6 7 8 9 n n 1 Capture Timer Stop Clear Start Interrupt Interval Period Delay INT0IF Ext INT0 Pin Interrupt Request INT0IF This value is loaded to CDR0 Interrupt Interval Period FFH 0...

Page 56: ...R31 PWM pin operates as a 10 bit res olution PWM output port For this mode the bit PWM of Port Mode Register PMR and the bit PWME of timer1 mode register TM1 should be set to 1 respectively The period...

Page 57: ...rce Clock PWM Duty PWMHR 1 0 T1PDR 1 X Source Clock If it needed more higher frequency of PWM it should be reduced resolution Note If the duty value and the period value are same the PWM output is det...

Page 58: ...80 81 3FF 01 02 POL 1 PWM POL 0 Duty Cycle 80H 1 x 250nS 32 25uS Period Cycle 3FFH x 250nS 256uS 3 9kHz PWMHR 0CH T1PPR FFH T1PDR 80H T1CK 1 0 00 250nS PWM03 PWM02 PWM01 PWM00 T1PPR 8 bit T1PDR 8 bit...

Page 59: ...llate even when the CPU is in the STOP mode The timer counter consists of 21 bit binary counter and it can count to max 64 seconds at sub clock The bit 2 3 of WTMR select the interrupt request interva...

Page 60: ...the watch should be kept work ing follow the steps below 1 Determines which mode is to be performed between main mode and sub mode when the MCU is released from Stop mode and set the clock source of w...

Page 61: ...the result is loaded into the ADDR the A D conversion status bit ADF is set to 1 and the A D interrupt flag ADIF is set The block diagram of the A D module is shown in Figure 14 1 The A D status bit A...

Page 62: ...function as input output port PORT R2 pins When A D conversion is per formed with any of pins AN0 to AN3 selected be sure not to execute a PORT input instruction while conversion is in progress as th...

Page 63: ...l lowing as shown below The bits BCK1 BCK0 of BDR select the source clock from prescaler output fBUZ BUZ pin frequency Prescaler ratio Prescaler divide ratio by BDR 7 6 BCD value 6 bit compare data BC...

Page 64: ...841 2 604 2 404 2 232 2 083 1 953 28 29 2A 2B 2C 2D 2E 2F 6 098 5 952 5 814 5 682 5 556 5 435 5 319 5 208 3 049 2 976 2 907 2 841 2 778 2 717 2 660 2 604 1 524 1 488 1 453 1 420 1 389 1 359 1 330 1 3...

Page 65: ...Mode 00 Normal Port R05 R06 R07 01 Transmit Mode SCK SO R07 10 Receive Mode SCK R06 SI 11 Transmit Receive Mode SCK SO SI SIOST Serial I O Operation Start Control 0 SIO Operation Stop 1 SIO Operation...

Page 66: ...1 Data Transmit Receive Timing The SCI operation is executed by setting the SIOST bit to 1 The SIOST bit is cleared to 0 automatically after 1 machine cycle The Serial output data is shift in or shif...

Page 67: ...l transmission If both transmission mode is selected and transmission is per formed simultaneously it would be made error 4 The SIO interrupt is generated at the completion of SIO and SIOSF is set to...

Page 68: ...R Table 17 1 Interrupt Priority Figure 17 1 Block Diagram of Interrupt Function Reset Interrupt Symbol Priority Vector Addr Hardware Reset Key Scan Interrupt BIT Interrupt External Interrupt 0 Externa...

Page 69: ...the completion of the current in struction execution The interrupt service task is terminat ed upon execution of an interrupt return instruction RETI Interrupt acceptance 1 The interrupt master enable...

Page 70: ...data memory area for saving registers The following method is used to save restore the general purpose registers Example Register saving General purpose registers are saved or restored by using push a...

Page 71: ...enerally when an interrupt is accept ed the I flag is cleared to disable any further interrupt But as user sets I flag in interrupt routine some further inter rupt can be serviced even if certain inte...

Page 72: ...twelve cycles Thus a max imum of twelve complete machine cycles elapse between activation of an external interrupt request and the begin ning of execution of the first instruction of the service rou...

Page 73: ...agram Usage of Key Scan When key board scanning it is recommended that set the output strobe to L first and then read R1 port after 60us delay time Because the rising time of the output strobe port fr...

Page 74: ...ins connected with LCD 1 Segment output port 37 pins SEG0 SEG36 2 Common output port 4 pins COM0 COM3 19 1 Configuration of LCD driver Figure 19 1 shows the configuration of the LCD driver Figure 19 1...

Page 75: ...ub clock is stabilized It is recom mended to use LCD display on after the stabilization time of sub clock is considered enough If the LCD is reset dur ing display the display would be blotted by the c...

Page 76: ...is location that are not used for LCD display can be allocated for general purpose use The SEG data for display is controlled by RPR RAM Pag ing Register Figure 19 4 Setting of RAM Paging Register Fig...

Page 77: ...e as those shown is Fig ure 19 7 Following is showing the Programming example for displaying character Note When power on RESET sub oscillation start up time is required Enable LCD display after sub o...

Page 78: ...XCN STA X UPPER 4 BITS OF ACC seg1 CLRG Set Page 0 FONT DB 1101_0111B 0 DB 0000_0110B 1 DB 1110_0011B 2 DB 1010_0111B 3 DB 0011_0110B 4 DB 1011_0101B 5 DB 1111_0101B 6 DB 0000_0111B 7 DB 1111_0111B 8...

Page 79: ...timer The content of the RODR 0 is output to the REMOUT pin Namely the REMOUT pin outputs a high level signal when RODR 0 is 1 and a low level signal when RODR 0 is 0 Figure 20 1 Remocon Carrier Gene...

Page 80: ...cy Low Selection ADDRESS 0F8H CFL5 CFL4 CFL3 CFL2 CFL1 CFL0 Bit 7 6 5 4 3 2 1 0 W W W W W W RESET VALUE 111111B Carrier Low Interval The Value of CFLS x Clock Source Period RESET VALUE 11111111B Remoc...

Page 81: ...7 00 8 00 9 00 10 00 11 00 12 00 13 00 14 00 15 00 16 00 17 00 18 00 19 00 20 00 21 00 22 00 23 00 24 00 25 00 26 00 27 00 28 00 29 00 30 00 31 00 1 00 2 00 3 00 4 00 5 00 6 00 7 00 8 00 9 00 10 00 11...

Page 82: ...s CLR1 ROD0 LDM R_bit 1111_1000B LDM RDHR 213 213 5 PS5 8us 8 52ms LDM RDLR 177 177 3 PS5 8us 4 248ms LDX 9 CALL DATA SET1 RMR 6 Remocon operation enable SET1 RMR 3 Remocon data pulse enable SET1 IENL...

Page 83: ...on see Figure 21 2 for the layout of the crystal Note Minimize the wiring length Do not allow the wiring to intersect with other signal conductors Do not allow the wir ing to come near changing high c...

Page 84: ...ndeterminate Therefore this RAM should be initialized before read or tested it When the RESET pin input goes to high the reset opera tion is released and the program execution starts at the vec tor ad...

Page 85: ...ted Figure 23 1 Low Voltage Detector Register Figure 23 2 Power Fail Processor Situations The values of 1 7V and 2 2V could be changed by 0 2V according to the process of work R W R W R W R W SYCC 1 0...

Page 86: ...4 The Choice Sigma is a Hynix Universal Single Programmer for all of Hynix OTP devices also the Choice Gang4 can program four OTPs at once for Hynix OTP Ask to Hynix sales part for purchasing or more...

Page 87: ...2 SEG0 SEG47 SEG45 SEG43 SEG41 SEG39 SEG37 COM0 COM2 S35 SEG33 SEG31 SEG29 SEG27 SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 SEG7 SEG5 SEG3 SEG1 GND VCL1 VLCDC CB GND REMOUT TONED GND R36 R34...

Page 88: ...on these switches 4 5 6 LCD Voltage booster circuit Must be ON position It is used for the GMS81C5108 7 Select the Stack Page Must be OFF position This switch decide the Stack page 0 off or page 1 on...

Page 89: ...her purpose Must be OFF position VR1 Adjust the LCD contrast It control the VCL2 voltage Refer to above SW4 1 2 3 figure Adjust the proper position as well as LCD display good VR2 Reserved for other p...

Page 90: ...GMS81C5108 JUNE 2001 Ver 1 0 87 Book History This Book Ver 1 0 JUNE 2001 First edition Downloaded from Elcodis com electronic components distributor...

Page 91: ...APPENDIX Downloaded from Elcodis com electronic components distributor...

Page 92: ...trol register R3CR W 0 0 0 0 33 00D8 Ext interrupt edge selection register IESR R W 0 0 0 0 0 0 69 00D9 Port selection register PMR R W 0 0 0 0 0 0 32 00DA Interrupt enable low register IENL R W 0 0 0...

Page 93: ...0F7 Carrier frequency high selection CFHS W 1 1 1 1 1 1 76 00F8 Carrier frequency low selection CFLS W 1 1 1 1 1 1 76 00F9 Remocon data high register RDHR W 1 1 1 1 1 1 1 1 76 00FA Remocon data low re...

Page 94: ...bit Bit Position A bit Bit Position of Accumulator dp bit Bit Position of Direct Page Memory M bit Bit Position of Memory Data 000H 0FFFH rel Relative Addressing Data upage U page 0FF00H 0FFFFH Offset...

Page 95: ...dp X STA abs TAX STY dp TCALL 14 STC M bit STX dp STX dp Y XAX STOP LOW HIGH 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1A 11011 1B 11100 1C 11101...

Page 96: ...5 21 CMP imm 44 2 2 Compare accumulator contents with memory contents A M 22 CMP dp 45 2 3 23 CMP dp X 46 2 4 24 CMP abs 47 3 4 N ZC 25 CMP abs Y 55 3 5 26 CMP dp X 56 2 6 27 CMP dp Y 57 2 6 28 CMP X...

Page 97: ...7 OR abs 67 3 4 N Z 68 OR abs Y 75 3 5 69 OR dp X 76 2 6 70 OR dp Y 77 2 6 71 OR X 74 1 3 72 ROL A 28 1 2 Rotate left through Carry 73 ROL dp 29 2 4 N ZC 74 ROL dp X 39 2 5 75 ROL abs 38 3 5 76 ROR A...

Page 98: ...register auto increment M A X X 1 27 STX dp EC 2 4 Store X register contents in memory 28 STX dp Y ED 2 5 M X 29 STX abs FC 3 5 30 STY dp E9 2 4 Store Y register contents in memory 31 STY dp X F9 2 5...

Page 99: ...y MM Z 4 BIT abs 1C 3 5 Z A M N M7 V M6 5 CLR1 dp bit y1 2 4 Clear bit M bit 0 6 CLRA1 A bit 2B 2 2 Clear A bit A bit 0 7 CLRC 20 1 2 Clear C flag C 0 0 8 CLRG 40 1 2 Clear G flag G 0 0 9 CLRV 80 1 2...

Page 100: ...then pc pc rel 11 BRA rel 2F 2 4 Branch always pc pc rel 12 BVC rel 30 2 2 4 Branch if overflow bit clear if V 0 then pc pc rel 13 BVS rel B0 2 2 4 Branch if overflow bit set if V 1 then pc pc rel 14...

Page 101: ...POP A 0D 1 4 sp sp 1 A M sp 6 POP X 2D 1 4 sp sp 1 X M sp 7 POP Y 4D 1 4 sp sp 1 Y M sp 8 POP PSW 6D 1 4 sp sp 1 PSW M sp restored 9 PUSH A 0E 1 4 M sp A sp sp 1 10 PUSH X 2E 1 4 M sp X sp sp 1 11 PU...

Page 102: ...Check sum Tel Fax Name Signature E mail address YYYY MM DD Approval date I agree with your verification data and confirm you to make mask set Tel Fax Name Signature E mail address UD FEB 2001 GMS81C51...

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