GMS81C5108
JUNE 2001 Ver 1.0
35
The system clock is decided by bit1 of the system clock
mode register, SCMR. In selection Sub clock, to oscillate
or stop the Main clock is decided by bit0 of SCMR.
On the initial reset, internal system clock is PS1 which is
the fastest and other clock can be provided by bit2 and bit3
of SCMR.
Figure 10-2 SCMR : System Clock Control Registers
R/W
R/W
R/W
R/W
SYCC[1:0] (System clock control)
00: main clock on
01: main clock on
10: sub clock on (main clock on)
11: sub clock on (main clock off)
SCS[1:0] (System clock source select)
00: f
MAIN
÷
2
01: f
MAIN
÷
8
INITIAL VALUE: 00
H
ADDRESS: 0F5
H
SCMR (System Clock Mode Register)
10: f
MAIN
÷
16
11: f
MAIN
÷
64
MSB
LSB
or f
SUB
÷
2
or f
SUB
÷
8
or f
SUB
÷
16
or f
SUB
÷
64
R/W
R/W
R/W
R
SVD[1:0] (SVD Flag)
SVD0 : set at VDD=2.2V
SVD1 : set at VDD=1.7V
SVRT (System Reset Control by SVD1 Bit)
0 : System reset by SVD1 Flag
1 : Don’t system reset by SVD1 Flag (Freeze)
SVEN (SVD Operation Enable Bit)
0 : SVD Operation Enable
1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by ±0.2V according to the process of work.
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