Huahuan Electronics H0FL-EthMux.SA1601, User Manual

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Beijing Huahuan Electronics Co., Ltd.
H0FL-EthMux.SA1601/SA1602 User’s Manual V1.3
7
Table 1.3-1 Timing mode schemes
A side
device clock
mode B side device
clock mode A side
EthMux
timing mode B side
EthMux
timing mode Remark
Master clock Master clock Loopback Loopback
Device clocks at
A and B sides
are synchronous
Adaptive Adaptive
Master clock Master clock Adaptive Adaptive Device clocks at
A and B sides
are respectively
independent
Master clock Slave clock Loopback Adaptive -
Adaptive Adaptive
Slave clock Master clock Adaptive Loopback -
Adaptive Adaptive
Slave clock Slave clock - - Not allowed
2
2
.
.


S
S
y
y
s
s
t
t
e
e
m
m
A
A
r
r
c
c
h
h
i
i
t
t
e
e
c
c
t
t
u
u
r
r
e
e
2.1 Function Introduction
H0FL-EthMux.SA1601/SA1602 is built on TDM/Packet processing unit. It
truncates E1/T1 data stream and encapsulates the data into Ethernet packet; and
then sends the packed MAC frame to the Ethernet exchange unit via MII
interface; finally, accesses to Ethernet network through uplink Ethernet ports.
The receiving end sends Ethernet data packets carried with E1/T1 data to
the TDM/Packet processing unit via MII interface. The processing unit will
reassemble the receiving packets to recover the original E1/T1 data stream and
outputs it via E1/T1 interface unit. TDM/Packet processing unit needs to process