HP PCIe U320, User Manual

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Glossary
ANSI American National Standards Institute
arbitrate Process of selecting one L_Port from a collection of ports which ask for use of
the arbitrated loop at the same time.
Asynchronous
Information Pro-
tection
AIP: although most Ultra320 traf fi c is sent synchronously and protected by CRC,
some information is still sent asynchronously. AIP implements CRC-level error
checking on asynchronous traf fi c ensuring end-to-end data integrity.
autonegotiation hardware senses and automatically responds depending on con fi guration
BER Bit Error Rate. A measure of transmission accuracy; the ratio of bits received in
error to bits sent.
bit Smallest unit of data a computer can process: a single binary digit with a
value of either 0 or 1.
bus a collection of unbroken signal lines used to transmit information from one part
of a computer system to another. Taps on the lines connect devices to the bus.
byte an ordered set of 8 bits
channel a point-to-point link which transports data from one point to another.
CPU Central Processing Unit. The portion of the computer that performs computations.
CRC Cyclic Redundancy Checking, an error-correcting code which calculates a
numeric value for received and transmitted data. If no error has occurred
during transmission, the CRC for both received and transmitted data should
be the same.
destination ad-
dress
A value in the frame header of each frame which identi fi es the port in the node
where the frame is being sent
device driver A program that allows a microprocessor to direct the operation of a peripheral
device.
DMA
Direct Memory Access. A way to move data from a storage device directly to
RAM without using the CPU's resources.
DMA bus master Allows a peripheral to control the fl ow of data to and from system memory by
block as opposed to allowing the processor to control the data by bytes (PIO
or programmed I/O).
domain validation Before sending data, domain validation veri fi es that the physical connection is
capable of handling the negotiated transfer speed. If the system determines that
Ultra320 speeds are not feasible, a slower speed is enforced.
double transition
clocking
Increases the data line frequency to equal that of the request signal, allowing
sampling on both the leading and trailing edges of the request signal. Clocking
can be set to ensure compatibility with legacy devices.
fl ow control The target indicates to the initiator when the last packet of a data stream will be
transferred so that the initiator can fl ush FIFOs and terminate pre-fetch sooner
than previously possible. Basically, the target warns the initiator that the transfer
User guide
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