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2 System Board
Host Bus
accept another request. The MCH, as target device, then requests the bus
again when it is ready to respond, and sends the requested data packet. Up
to four transactions are allowed to be outstanding at any given time.
For the Host bus to run at 133 MHz while respecting the specified signal and
timings, a distributed mechanism is used on each AGTL+ signal. The bus is
routed with a “Y” topology.
Intel Pentium III Processor
HP Kayak XM600 PC Workstations
are supplied with a Pentium III
processor and an integrated VRM (Voltage Regulator Module) on the system
board. Because these PC Workstations do not have any VRM sockets, a VRM
does not need to be installed.
The Pentium III processor has several features that enhance performance:
•
Dual Independent Bus architecture, which combines a dedicated 64-bit
L2 cache bus (supporting level cache sizes of i256 KB or 512 KB) plus a
64-bit system bus.
•
MMX technology, which gives higher performance for media,
communications and 3D applications.
•
Dynamic execution to speed up software performance.
•
Internet Streaming SIMD Extensions for enhanced floating point and 3D
application performance.
•
Processor Serial Number is an electronic number incorporated in the
processor. If enabled, the Processor Serial Number can serve as a means
of identifying the system. By default, this option is set to Disabled in the
Setup
program.
•
Uses multiple low-power states, such as AutoHALT, Stop-Grant, Sleep and
Deep Sleep to conserve power during idle times.
The Pentium III processor (core and cache memory) is packaged in a
self-contained Single Edge Contact Cartridge (SECC-2) installed in a Slot 1
processor slot. The SECC-2 cartridge requires a 242-contact Slot 1
connector on the system board. It includes a processor core chip, tag and
data SRAMS, and AGTL+ termination resistors.
Processor Clock
The 100/133 MHz Host Bus clock is provided by a PLL. The processor core
clock is derived from the Host Bus by applying a “ratio”. This ratio is
programmed by the system board. The processor then applies this ratio to
the Host Bus clock to generate its CPU core frequency.
