43
2 System Board
Memory Controller Hub (MCH) 82820
The following table shows the features that are available in the MCH Host
Bridge/Controller.
Feature
Feature
•
Processor/Host Bus:
❒
Supports Pentium III processor configuration at both 100
MHz and133 MHz bus speeds
❒
Supports Symmetric Multiprocessing Protocol (SMP) for up
to two processors
❒
APIC related buffer management support
❒
Supports 32-bit host bus addressing
❒
Supports 6-deep In-Order Queue
❒
AGTL+ bus driver technology (gated)
❒
AGTL+ receivers for reduced power
❒
Supports single-ended AGTL+ termination in uniprocessor
configuration
•
Accelerated Graphics Port (AGP) Interface:
❒
Supports a single AGP device (either via a connector or on
the system board)
❒
Supports AGP 2.0, including 1x/2x/4x AGP data transfers,
1.5V and 3.3V signaling, and 2x/4x Fast Write protocol
❒
AGP Universal Connector support via dual mode buffers
❒
AGP PIPE# or SB accesses to DRAM not snooped
❒
AGP FRAME# accesses to DRAM are snooped
❒
High priority access support
❒
Hierarchical PCI configuration mechanism
❒
Delayed transaction support for AGP-to-DRAM reads using
AGP FRAME# protocol
•
Memory Controller
Direct Rambus:
•
Direct Rambus Memory Controller, supporting:
❒
Single Direct Rambus Channel
❒
Supports PC700, and PC800 Direct Rambus DRAM modules
❒
Maximum memory array size up to 256 MB using
64Mb/72Mb, 512 MB using 128Mb/144Mb, 1 GB using
256Mb/288Mb DRAM technology
❒
Supports up to 32 Direct Rambus devices per channel
❒
Supports a maximum DRAM address decode space of 4 GB
❒
Configurable optional ECC operation:
- ECC with single bit Error Correction and multiple bit Error
Detection
- Single bit errors corrected and written back to memory (au-
to-scrubbing)
- Parity mode not supported
SDRAM:
❒
Up to 1 GB of SDRAM
❒
Interleaved 100 MHz support.
❒
Non-Interleaved 100 MHz support.
❒
Both registered and unbuffered DIMMs are supported.
❒
Up to 4 rows or 2 DS DIMMs per MTH.
❒
Up to 8 simultaneous open pages:
— 2 KByte page size support for 64 Mbit SDRAM devices.
— 4 KByte - 16 KByte page sizes supporting 64 MBit to
256 Mbit SDRAM devices.
•
Hub Link 8-bit Interface to ICH:
❒
Private interconnect between the MCH and ICH.
