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2 System Board
Memory Controller Hub (MCH) 82820
MCH Interface
The MCH interface provides bus control signals and address paths for
transfers between the processors on the Host bus (FSB), Direct Rambus
channel and AGP 4x bus.
The MCH allows the processor to access up to 4 GB of memory. It also
provides an 8-deep In-Order Queue supporting up to eight outstanding
transaction requests on the host bus.
The MCH can support one or two Pentium III processors, at FSB frequencies
of 100/133 MHz using GTL+ signalling. Refer to
page 66
for a description of
the devices on the Host bus.
Accelerated Graphics Port (AGP) Bus Interface
A controller for the AGP4x (Accelerated Graphics Port) slot is integrated in
the MCH. The AGP Bus interface is compatible with the Accelerated
Graphics Port Specification, Rev 2.0, operating at 133 MHz, and supporting
up to 1 GB/sec data transfer rates. The MCH supports only a synchronous
AGP interface, coupling to the Host bus frequency.
•
Power Management:
❒
SMRAM space re-mapping to A0000h (128 KB)
❒
Supports HSEG and TSEG cacheable extended SMRAM
space
- 128 KB HSEG at 0FEEA0000h remapped to A0000h
- TSEG is 128 KB/256 KB/512 KB/1 MB at the top of memory
- No maximum DRAM limit to use extended SMM
❒
SMRAM accesses from AGP or the hub interface are not al-
lowed
❒
Suspend to DRAM (STR) support
❒
ACPI Rev 1.0 compliant power management
❒
APM Rev 1.2 compliant power management
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Arbitration:
❒
Distributed Arbitration Model for Optimum Concurrency
Support.
❒
Concurrent operations of host, hub interface, AGP and
memory buses supported via a dedicated arbitration and
data buffering logic.
•
324-pin BGA MCH package.
•
Input/Output Device Support:
❒
Input/Output Controller Hub (ICH).
Feature
Feature
