HP 85662A, Troubleshooting And Repair Manual

Page: 243 / 594

output with 0 V input. U5 compares the input and output of the Peak Detector. A TTL high
level is produced when the output is greater than the input. (R40, R41, and provide a
small amount of hysteresis for noise immunity.)
Negative Peak Detector
The Negative Peak Detector acquires the most negative voltage to appear at its input and
holds that voltage on holding capacitor C38 until reset by a pulse from the decoding and
timing circuits. Circuit operation is the same as that of the Positive Peak Detector except
that supply polarities are reversed and PNP instead NPN transistors are used. Figure 2 shows
a simplified schematic of the Negative Peak Detector.
R 2 0
FROM
Figure 2. Negative Peak Detector, Simplified Schematic
The circuit consists of amplifier diode CR2, holding capacitor C38, buffer
and reset transistor Q12. R71 creates an offset between the output and the emitter
of This insures that the voltage across C38 is always negative for positive outputs from
0 V to V. GNEG potentiometer R52 sets the gain (input attenuation) so that a 2 V
full-scale input produces a 1 V full-scale output. OFS NEG potentiometer R36 zeroes the
offset. U4 compares the input to the output.
Decoding and Timing
The Decoding and Timing circuit provides reset pulses to the Peak Detectors and control lines
for Multiplexer selection, and it performs other logic functions.
decodes control lines SEL A and SEL B to produce three lines for Multiplexer selection.
After inversion by and the voltage levels are shifted to -0.5 V and V.
Multivibrators and produce pulses (when triggered by HOLD) which reset the
Peak Detectors. Latches and are used to provide the Peak Detector status signal
LTRK.
Multiplexer
The outputs of the Peak Detectors are multiplexed through before sampling by the Track
and Hold circuit. Control lines to the Multiplexer are provided by the Decoding and Timing
circuit.
2