24 SAS/SATA physical links distributed across six Mini SAS connectors
Two Mini SAS 4i connectors (8 physical links): for attachment to internal drive backplanes
Four Mini SAS 4x connectors (16 physical links): for attachment to JBODs and external tape
drives
Storage Interface
(SAS/SATA)
PCI-e 3.0 (8 GT/s)
Eight lane mechanical connector
Electrically supports one, four, and eight lanes
Host Interface
(PCI-e)
P822 includes a Sierra SRCv 8x6G SAS RAID-on-chip featuring:
Eight SAS/SATA physical links, each supporting 6 and3 Gb/s for SAS and SATA protocol
Eight PCI-e 3.0 lanes each supporting 8 Gb/s
DDR3-1600 MHz memory controller
High performance MIPS-based multi-processor subsystem
Hardware XOR and Reed-Solomon Engines for RAID 5 and RAID 6 acceleration
RAID Processor and
Expander
The P822 2GB array accelerator features a flash-backed write cache. If the cache DRAM contains data when
power is lost, the data is copied into flash memory of the cache module, drawing power from attached
capacitors. When power is restored, if the flash memory chips contain write data, the data is copied back
into the DRAM so it can be flushed to the drives.
Advantages over battery-backed cache architectures include:
No 72-hour deadline for retrieving the data before the batteries fully discharge
Capacitors charge faster than batteries; controller disables the write cache for only a few minutes
waiting for capacitors to charge rather than a few hours waiting for batteries to charge
No need for periodic battery replacement
No special disposal process
Interface Speeds
P822 supports the latest interface speed
Interface
Maximum bandwidth
*
Notes
PCI-e
8 GiB/s (in each direction)
PCI-e 3.0 (8 lanes at 8 GT/s)
SAS/SATA
14.4GiB/s (in each direction)
SAS-2 (24 physical links at 6 Gb/s)
RAID cache
2 GB/s
DDR3-1600 MHz SDRAM (64-bit data and 8-
bit ECC)
* Not counting protocol overhead.
QuickSpecs
HP Smart Array P822 Controller
Standard Features
DA - 14341 North America — Version 11 — September 10, 2013
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