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Summary of Contents for HT66F488

Page 1: ...A D Flash MCU with EEPROM HT66F488 HT66F489 Revision V1 21 Date November 09 2017 ...

Page 2: ...s 17 System Architecture 18 Clocking and Pipelining 18 Program Counter 19 Stack 20 Arithmetic and Logic Unit ALU 20 Flash Program Memory 21 Structure 21 Special Vectors 21 Look up Table 22 Table Program Example 22 In Circuit Programming 23 On Chip Debug Support OCDS 24 RAM Data Memory 25 Structure 25 General Purpose Data Memory 25 Special Purpose Data Memory 26 Special Function Register Descriptio...

Page 3: ...ernal 32kHz Oscillator LIRC 38 Supplementary Oscillator 38 Operating Modes and System Clocks 39 System Clocks 39 System Operation Modes 40 Control Register 41 Fast Wake up 42 Operating Mode Switching 43 Standby Current Considerations 45 Wake up 45 Programming Considerations 46 Watchdog Timer 46 Watchdog Timer Clock Source 46 Watchdog Timer Control Register 46 Watchdog Timer Operation 48 Reset and ...

Page 4: ...90 PTM register description 91 Periodic Type TM Operating Modes 95 Analog to Digital Converter 104 A D Overview 104 A D Converter Register Description 104 A D Converter Data Registers ADRL ADRH 105 A D Converter Control Registers ADCR0 ADCR1 ACERL 105 A D Operation 108 A D Input Pins 110 Summary of A D Conversion Steps 110 Programming Considerations 112 A D Transfer Function 112 A D Programming Ex...

Page 5: ...55 Multi function Interrupt 156 A D Converter Interrupt 156 Time Base Interrupts 156 Serial Interface Module Interrupts 157 EEPROM Interrupt 158 TM Interrupts 158 LVD Interrupt 158 UART Interrupt 158 Interrupt Wake up Function 159 Programming Considerations 159 Software LCD Driver 160 LCD operation 160 LCD Control Registers 160 LCD waveform 165 Low Voltage Detector LVD 167 LVD Register 167 LVD Ope...

Page 6: ... with EEPROM Instruction Set Summary 172 Table Conventions 172 Extended Instruction Set 174 Instruction Definition 176 Extended Instruction Definition 185 Package Information 192 28 pin SOP 300mil Outline Dimensions 193 28 pin SSOP 150mil Outline Dimensions 194 ...

Page 7: ...All instructions executed in one to three instruction cycles Table read instructions 115 powerful instructions 8 level subroutine nesting Bit manipulation instruction Peripheral Features Flash Program Memory 8K 16 HT66F489 4K 16 HT66F488 RAM Data Memory 384 8 True EEPROM Memory 64 8 Watchdog Timer function 30 bidirectional I O lines LED driver 1 3 Bias Software LCD Serial Interface Module SIM for ...

Page 8: ...llent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments A full choice of HXT LXT HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation The ability to operate and switch dynamically between a range of operating modes using different cl...

Page 9: ... PTP1 SCK SCL SSEG11 PA4 SDI SDA SSEG10 PA3 SDO SSEG9 PA2 OCDSCK SSEG8 PA1 SSEG7 PC6 AN6 VREF INT2 SSEG20 PB1 PTCK0 INT1 AN7 SSEG17 PB2 CTP INT0 SSEG16 PB3 OSC2 XT2 SSEG15 PB4 OSC1 XT1 ICPCK SSEG14 VDD AVDD PA7 CTCK SSEG13 PD1 SCOM1 SSEG1 PD2 SCOM2 SSEG2 PD3 SCOM3 SSEG3 PD4 SCOM4 SSEG4 PD5 SCOM5 SSEG5 PA0 OCDSDA SSEG6 HT66F488 489 HT66V488 489 28 SOP A SSOP A 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 10: ...utput PA5 PTP1 SCK SCL SSEG11 PA5 PAWU PAPU ST CMOS General purpose I O Register enable pull up and wake up PTP1 TMPC0 ST CMOS PTM1 input output SCK ST CMOS SPI Serial Clock SCL ST NMOS I2 C Clock SSEG11 SLCDC2 CMOS Software LCD SEG output PA6 PTCK1 SCS SSEG12 PA6 PAWU PAPU ST CMOS General purpose I O Register enable pull up and wake up PTCK1 ST PTM1 input SCS ST CMOS SPI slaver selection SSEG12 S...

Page 11: ...AN2 SSEG26 PC0 PCPU ST CMOS General purpose I O Register enable pull up AN2 ACERL AN ADC input SSEG26 SLCDC4 CMOS Software LCD SEG output PC1 SSEG25 PC1 PCPU ST CMOS General purpose I O Register enable pull up SSEG25 SLCDC4 CMOS Software LCD SEG output PC2 SSEG24 PC2 PCPU ST CMOS General purpose I O Register enable pull up SSEG24 SLCDC4 CMOS Software LCD SEG output PC3 AN3 SSEG23 PC3 PCPU ST CMOS ...

Page 12: ... output SSEG4 SLCDC1 CMOS Software LCD SEG output PD5 SCOM5 SSEG5 PD5 PDPU ST CMOS General purpose I O Register enable pull up SCOM5 SLCDC1 CMOS Software LCD COM output SSEG5 SLCDC1 CMOS Software LCD SEG output VDD AVDD VDD PWR Positive Power Supply AVDD PWR Analog Positive Power Supply VSS AVSS VSS PWR Negative Power Supply Ground AVSS PWR Analog Negative Power Supply Note I T Input type O T Outp...

Page 13: ...Operating Voltage HXT fSYS 8MHz 2 2 5 5 V fSYS 10MHz 2 7 5 5 V fSYS 12MHz 3 3 5 5 V fSYS 16MHz 4 5 5 5 V Operating Voltage HIRC fSYS 8MHz 2 2 5 5 V IDD Operating Current Normal Mode fSYS fH HXT fS fLIRC 3V No load fSYS fH 8MHz ADC off WDT enable 1 0 1 5 mA 5V 2 5 4 0 mA 3V No load fSYS fH 10MHz ADC off WDT enable 1 2 2 0 mA 5V 2 8 4 5 mA 5V No load fSYS fH 12MHz ADC off WDT enable 3 5 5 5 mA 5V No...

Page 14: ...VDD V IOL I O Port Sink Current Large Sink I O PD 5V VOL 1 5V 120 200 mA 3V VOH 0 1VDD 15 30 mA 5V VOH 0 1VDD 30 60 mA I O Port Sink Current PA PB PC 3V VOL 0 1VDD 15 30 mA 5V VOL 0 1VDD 30 60 mA IOH I O Port Source Current PA PB PC PD 3V VOH 0 9VDD select full source current option 3 0 6 0 mA VOH 0 9VDD select 10 22 full source current option 1 5 3 0 mA VOH 0 9VDD select 7 22 full source current ...

Page 15: ...60 kHz tTIMER xTCKn Input Pin Minimun Pulse width 0 06 0 15 0 3 μs tSST System Start up Timer Period wake up from HALT fSYS HXT 128 tSYS fSYS LXT 128 tSYS fSYS HIRC 16 tSYS fSYS LIRC 2 tSYS System Start up Timer Period wake up from HALT fSYS on at HALT 2 tSYS tRSTD System Reset Delay Time POR LVR LVR S W WDT S W reset 25 50 100 ms System Reset Delay Time WDT reset 8 3 16 7 33 3 ms tINT Interrupt M...

Page 16: ...2 V LVDEN 1 VLVD 2 4V 2 4 V LVDEN 1 VLVD 2 7V 2 7 V LVDEN 1 VLVD 3 0V 3 0 V LVDEN 1 VLVD 3 3V 3 3 V LVDEN 1 VLVD 3 6V 3 6 V LVDEN 1 VLVD 4 0V 4 0 V ILVR Additional Power Consumption if LVR is Used 3V LVR disable LVR enable 30 45 μA 5V 60 90 μA ILVD Additional Power Consumption if LVD is Used 3V LVD disable LVD enable LVR disable 40 60 μA 5V 75 115 μA 3V LVD disable LVD enable LVR enable 30 45 μA 5...

Page 17: ...y 3V 5V VREF VDD tAD 0 5μs Ta 40 C 85 C 4 4 LSB INL1 A D Integral Non linearity 2 2V 2 7V VREF VDD tAD 8μs Ta 25 C 16 LSB 2 7V 5 5V VREF VDD tAD 0 5μs Ta 25 C 4 4 LSB INL2 A D Integral Non linearity 3V 5V VREF VDD tAD 0 5μs Ta 40 C 85 C 6 6 LSB IADC Additonal Power consumption if A D Converter is used 3V No load tAD 0 5μs 1 0 2 0 mA 5V 1 5 3 0 mA tBGS VBG turn on stable time 10 ms VBG Bandgap refe...

Page 18: ...ng methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D control system with maximum reliability and flexibility This makes the device suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a HXT LXT HIRC ...

Page 19: ...s requiring jumps to non consecutive addresses such as a jump instruction a subroutine call interrupt or reset etc the microcontroller manages program control by loading the required address into the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy ...

Page 20: ...to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost P r o g r a m C o u n t e r S t a c k L e v e l 1 S t a c k L e v e l 2 S t a c k L e v e l 3 S t a c k L e v e l 8 P r o g r a m M e m o r y T o p o f S t a c k S t a c k P o i n t e r B o t t o m o f S t a c k Arithmetic and Logic Unit ALU The ar...

Page 21: ...e The Program Memory has a capacity of 4K 16 bits to 8K 16 bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be setup in any location within the Program Memory is addressed by a separate table pointer register Device Capacity HT66F488 4K 16 HT66F489 8K 16 0000H Reset Interrupt Vector 0004H 003CH 0FFFH 16 ...

Page 22: ...llowing example shows how the table pointer and table data is defined and retrieved from the microcontroller This example uses raw table data located in the Program Memory which is stored there using the ORG statement The value at this ORG statement is F00H which refers to the start address of the last page within the 4K words Program Memory of the HT66F488 device The table pointer is setup here t...

Page 23: ...ng the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later stage This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without remo...

Page 24: ...g function Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT IDE development tools The OCDSDA pin is the OCDS Data Address input output pin while the OCDSCK pin is the OCDS clock input pin When users use the EV chip for debugging other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU devic...

Page 25: ... Purpose Data Memory for all devices is the address 00H while the start address of the General Purpose Data Memory is the address 80H The Special Purpose Data Memory registers are accessible in all sectors with the exception of the EEC register at address 40H which is only accessible in Sector 1 Device Capacity Sectors HT66F488 HT66F489 General Purpose 384 8 0 80H FFH 1 80H FFH 2 80H FFH Special P...

Page 26: ...AWU MFI1 MFI2 PAPU PA PAC PB PBC PCPU PCC PDPU PD IOHR IOHR1 ADRH ADCR ADCR1 TMPC CTMC CTMC1 2 H 21H 22H 2 H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 25H 26H 2 H 3 H 31H 32H 3 H 38H 3BH 3AH 3DH 3CH 3FH 3EH 33H 34H 35H 36H 3 H 4 H EEC 41H EEA 42H EED 43H PTM1RPL 4 H PTM1RPH 48H PTM RPH 4 H I TEG 4AH I TEG1 4BH WDTC 4CH TBC 4DH PTM1AL 4EH PTM1AH 4FH 5 H 51H 52H 58H 53H 54H 55H 56H 5 H Secto 2 Secto 1 Unu...

Page 27: ...L MP2H register pair can access data from any Data Memory sector As the Indirect Addressing Registers are not physically implemented reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation Memory Pointers MP0 MP1L MP1H MP2L MP2H Five Memory Pointers known as MP0 MP1L MP1H MP2L and MP2H are provided These M...

Page 28: ...y location has been cleared jmp loop continue Indirect Addressing Program Example 2 data section at 01F0H data adres1 db adres2 db adres3 db adres4 db block db code section at 0 code org00h start mov a 04h setup size of block mov block a mov a 01h setup the memory sector mov mp1h a mov a offset adres1 Accumulator loaded with first RAM address mov mp1l a setup memory pointer with first RAM address ...

Page 29: ... the table data is located Their value must be setup before any table read commands are executed Their value can be changed for example using the INC or DEC instructions allowing for easy table data pointing and reading TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed Note that the lower order table data byte is transf...

Page 30: ...ch is performed by the OV flag and the MSB of the instruction operation result Bit 6 CZ The the operational result of different flags for different instructions For SUB SUBM LSUB LSUBM instructions the CZ flag is equal to the Z flag For SBC SBCM LSBC LSBCM instructions the CZ flag is the AND operation result which is performed by the previous operation CZ flag and current operation zero flag For o...

Page 31: ...ions to the EEPROM are carried out in single byte operations using an address and data register in Sector 0 and a single control register in Sector 1 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control register EEC As both the EEA and EED registers are located in all sectors ...

Page 32: ...lication program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM Read Enable 0 Disable 1 Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out Clearing ...

Page 33: ...n internal timer whose operation is asynchronous to microcontroller system clock a certain time will elapse before the data will have been written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR bit will be automatically cleared to zero by the micr...

Page 34: ...IDLE or SLEEP mode until the EEPROM read or write operation is totally complete Otherwise the EEPROM read or write operation will fail Programming Examples Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1L MOV MP1L A MP1 points to EEC register MOV A 01H setup memory pointer MP1H MOV MP1H A SET IAR1 1 set RDEN bit enab...

Page 35: ...ystem clock the device has the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Freq Pins External Crystal HXT 400kHz 20MHz OSC1 OSC2 Internal High Speed RC HIRC 8MHz External low speed Crystal LXT 32 768kHz XT1 XT2 Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are four method...

Page 36: ...via configuration option For most crystal oscillator configurations the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation without requiring external capacitors However for some crystal types and frequencies to ensure oscillation it may be necessary to add two small value capacitors C1 and C2 Using a ceramic resonator will usually...

Page 37: ...re precise frequencies are essential these components may be required to provide frequency compensation due to different crystal manufacturing tolerances During power up there is a time delay associated with the LXT oscillator waiting for it to start up When the microcontroller enters the SLEEP or IDLE Mode the system clock is switched off to stop microcontroller activity and to conserve power How...

Page 38: ...lications such as battery applications where power consumption must be kept to a minimum it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power on It should be noted that no matter what condition the LXTLP bit is set to the LXT oscillator will always function normally the only difference is that it will take more time to start up if in the Low ...

Page 39: ...ster The high speed system clock can be sourced from either an HXT or HIRC oscillator selected via a configuration option The low speed system clock source can be sourced from internal clock fL If fL is selected then it can be sourced by either the LXT or LIRC oscillator selected via a configuration option The other choice which is a divided version of the high speed system oscillator has a range ...

Page 40: ...a mode where the microcontroller operates normally although now with a slower speed clock source The clock source used will be from the low speed oscillator LIRC or LXT Running the microcontroller in this mode allows it to run with much lower operating currents In the SLOW Mode 0 the fH is off SLOW1 Mode This is also a mode where the microcontroller operates normally although now with a slower spe...

Page 41: ...rce which can be the LIRC or LXT a divided version of the high speed system oscillator can also be chosen as the system clock source Bit 4 FSTEN Fast Wake up Control only for HXT 0 Disable 1 Enable This is the Fast Wake up Control bit which determines if the fSUB clock source is initially used after the device wakes up When the bit is high the fSUB clock source can be used as a temporary system cl...

Page 42: ...0 Bit 2 LVRF LVR function reset flag Describe elsewhere Bit 1 LRF LVRC register software reset flag Describe elsewhere Bit 0 WRF WDTC register software reset flag Describe elsewhere Fast Wake up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode where the system clock source to the device will be stopped However when the device is woken up again it can take a considerable t...

Page 43: ...Modes is executed via the HALT instruction When a HALT instruction is executed whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register When the HLCLK bit switches to a low level which implies that clock source is switched from the high speed clock source fH to the clock source fH 2 fH 64 or fL If...

Page 44: ...s time for full mode switching Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0 and the WDT on When this instruction is executed under the conditions described above the following will occur The system clock and Time Base clock will be stopped an...

Page 45: ...high or low level as any floating input pins could create internal oscillations and result in increased current consumption This also applies to devices which have different package types as there may be unbonbed pins These must either be setup as outputs or if setup as inputs must have pull high resistors connected Care must also be taken with the loads which are connected to I O pins which are s...

Page 46: ...n up from the SLEEP Mode and the HIRC oscillators need to start up from an off state If the device is woken up from the SLEEP Mode to NORMAL Mode and the system clock source is from HXT oscillator and FSTEN is 1 the system clock can be switched to the LIRC or LXT oscillator after wake up There are peripheral functions such as TMs for which the fSYS is used If the system clock source is switched fr...

Page 47: ...od selection 000 28 fSUB 001 210 fSUB 010 212 fSUB 011 214 fSUB 100 215 fSUB 101 216 fSUB 110 217 fSUB 111 218 fSUB These three bits determine the division ratio of the Watchdog Timer sourece clock which in turn determines the timeout period CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON LVRF LRF WRF R W R W R W R W R W POR 0 0 0 0 Bit 7 FSYSON fSYS Control IDLE Mode Describe elsewhere Bit 6 3 Unim...

Page 48: ...out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a Watchdog Timer time out occurs the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset Three methods can be adopted to clear the contents of the Watchdog Timer The first is a WDT reset which means a value other than 01010B and 101...

Page 49: ... well as ensuring that the Program Memory begins execution from the first memory address a power on reset also ensures that certain other registers are preset to known conditions All the I O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs Note tRSTD is power on delay typical time 50ms Power On Reset Timing Chart Low Voltage Reset...

Page 50: ... W POR 0 0 0 0 Bit 7 FSYSON fSYS Control IDLE Mode Describe elsewhere Bit 6 3 Unimplemented read as 0 Bit 2 LVRF LVR function reset flag 0 Not occur 1 Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs This bit can only be cleared to zero by the application program Bit 1 LRF LVRC register software reset flag 0 Not occur 1 Occurred This bit is set to 1 if the...

Page 51: ...RESET Conditions 0 0 Power on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time out reset during NORMAL or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation Note u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power on reset occurs Item Condition After RESET Pro...

Page 52: ...0 11 0 111 u u u u u u u u INTC0 000 0000 000 0000 000 0000 u u u u u u u INTC1 0000 0000 0000 0000 0000 0000 u u u u u u u u INTC2 0000 0000 0000 0000 0000 0000 u u u u u u u u INTC3 0000 0000 0000 0000 0000 0000 u u u u u u u u MFI0 00 00 00 00 00 00 u u u u MFI1 0 00 00 0 00 00 0 00 00 u u u u u MFI2 0000 0000 0000 0000 0000 0000 u u u u u u u u PAWU 0000 0000 0000 0000 0000 0000 u u u u u u u ...

Page 53: ...000 0000 0000 0000 0000 u u u u u u u u PTM0C0 0000 0 0000 0 0000 0 u u u u u PTM0C1 0000 0000 0000 0000 0000 0000 u u u u u u u u PTM0DL 0000 0000 0000 0000 0000 0000 u u u u u u u u PTM0DH 00 00 00 u u PTM0AL 0000 0000 0000 0000 0000 0000 u u u u u u u u PTM0AH 00 00 00 u u PTM0RPL 0000 0000 0000 0000 0000 0000 u u u u u u u u PTM0RPH 00 00 00 u u PTM1C0 0000 0 0000 0 0000 0 u u u u u PTM1C1 000...

Page 54: ...Data Memory with specific addresses as shown in the Special Purpose Data Memory table All of these I O ports can be used for input and output operations For input operation these ports are non latching which means the inputs must be ready at the T2 rising edge of instruction MOV A m where m denotes the port address For output operation all the data is latched and remains unchanged until the output...

Page 55: ... the I O ports is directly mapped to a bit in its associated port control register For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the logic state of the input pin to be directly read by instructions When the corresponding bit of the control register is written as a 0 the I O pin will be setup as a CMOS output If the...

Page 56: ...Rev 1 21 56 November 09 2017 HT66F488 HT66F489 A D Flash MCU with EEPROM Generic Input Output Structure A D Input Output Structure ...

Page 57: ...e current output 01 10 22 full source current output 10 7 22 full source current output 11 4 22 full source current output Bit 1 0 IOHS01 IOHS00 PA0 source current output selection bit 00 Full source current output 01 10 22 full source current output 10 7 22 full source current output 11 4 22 full source current output IOHR1 Register Bit 7 6 5 4 3 2 1 0 Name IOHS71 IOHS70 IOHS61 IOHS60 IOHS51 IOHS...

Page 58: ...nt output 11 4 22 full source current output Bit 3 2 IOHS91 IOHS90 PB4 PB7 source current output selection bit 00 Full source current output 01 10 22 full source current output 10 7 22 full source current output 11 4 22 full source current output Bit 1 0 IOHS81 IOHS80 PB0 PB3 source current output selection bit 00 Full source current output 01 10 22 full source current output 10 7 22 full source c...

Page 59: ...s Single or multiple pins on Port A can be setup to have this function Timer Modules TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time To implement time related functions the device includes several Timer Modules abbreviated to the name TM The TMs are multi purpose timing units and serve to provide operations such as Timer Counter Inp...

Page 60: ...internal comparator A or comparator P which generate a TM interrupt when a compare match condition occurs When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin TM External Pins Each of the TMs irrespective of what type has one TM input pin with the label xTCKn The TM input pin is essentially a clock source for the TM and is selected ...

Page 61: ...o the pin will retain its original other function TMPC0 Register Bit 7 6 5 4 3 2 1 0 Name PTP1CP0 PTP0CP0 STPCP0 CTPCP0 R W R W R W R W R W POR 0 0 0 0 Bit 7 Unimplemented read as Bit 6 PTP1CP0 PTP1 pin Control 0 Normal I O 1 PTP1 function Bit 5 Unimplemented read as Bit 4 PTP0CP0 PTP0 pin Control 0 Normal I O 1 PTP0 function Bit 3 Unimplemented read as Bit 2 STPCP0 STP pin Control 0 Normal I O 1 ...

Page 62: ...STM STP STPCP0 PB7 data bit 1 0 1 0 STPCP0 0 STP STP STM Function Pin Control Block Diagram PTM Mode Controller PTM0 PTP0 PTP0CP0 PB0 data bit 1 0 1 0 PTP0CP0 0 PTP0 PTP0 PTM Mode Controller PTM1 PTP1 PTP1CP0 PA5 data bit 1 0 1 0 PTP1CP0 0 PTP1 PTP1 PTM0 PTM1 Function Pin Control Block Diagram ...

Page 63: ...ster named xTMnAL or PTMnRPL in the following access procedures Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values Data Bus 8 bit Buffer xTMnDH xTMnDL PTMnRPH PTMnRPL xTMnAH xTMnAL TM Counter Register Read only xTM CCRA Register Read Write PTMn CCRP Register Read Write The following steps show the read and write procedures Wri...

Page 64: ...compare the value in the counter with CCRP and CCRA registers The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changing the CTON bit from low to high The counter wi...

Page 65: ...hen in a Pause condition the TM will remain powered up and continue to consume power The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6 4 CTCK2 CTCK0 Select CTM Counter clock 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fTBC 101 fTBC 110 CTCK rising edge clock 111 CTCK falling edge clo...

Page 66: ...th the highest three counter bits the compare values exist in 128 clock cycle multiples Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value CTMC1 Register Bit 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 CTM1 CTM0 Select CTM Operating Mode 00 Compare Match Output Mod...

Page 67: ...1 Active high This is the output control bit for the TM output pin Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode It has no effect if the TM is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs In the PWM Mode it determines if the PWM signal is active h...

Page 68: ...W R R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 CTM Counter High Byte Register bit 1 bit 0 CTM 10 bit Counter bit 9 bit 8 CTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 CTM CCRA Low Byte Register bit 7 bit 0 CTM 10 bit CCRA bit 7 bit 0 CTMAH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W POR 0 0...

Page 69: ...However here only the CTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when CTCCLR is high no CTMPF interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the CTMAF interrupt request flag will not be generated As...

Page 70: ... Toggle Output Select Now CTIO 1 0 10 Active High Output Select Output not affected by CTMAF flag Remains High until reset by CTON bit CTCCLR 0 CTM 1 0 00 01 CTPAU Resume Stop Time CCRP 0 CCRP 0 CTPOL Output Pin Reset to initial value Output inverts when CTPOL is high un defined Counter Value Compare Match Output Mode CTCCLR 0 Note 1 With CTCCLR 0 a Comparator P match will clear the counter 2 The ...

Page 71: ...ed by CTMAF flag Remains High until reset by CTON bit CTCCLR 1 CTM 1 0 00 01 CTPAU Resume Stop Time CCRA 0 CTPOL Output Pin Reset to initial value Output inverts when CTPOL is high Counter Value Output does not change No CTMAF flag generated on CCRA overflow CCRA 0 Counter overflow CTMPF not generated un defined Compare Match Output Mode CTCCLR 1 Note 1 With CTCCLR 1 a Comparator A match will clea...

Page 72: ...veform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers An inter...

Page 73: ...et by CCRP Counter stop if CTON bit low Counter reset when CTON returns high PWM resumes operation Time CTDPX 0 CTM 1 0 10 CTPOL Output Inverts When CTPOL 1 CTPAU Resume Pause CTM O P Pin CTOC 0 un defined PWM Mode CTDPX 0 Note 1 Here CTDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues running even when CTIO 1 0 00 or 01 4 The CTCCLR bit has no i...

Page 74: ...od set by CCRA Counter stop if CTON bit low Counter reset when CTON returns high PWM resumes operation Time CTDPX 1 CTM 1 0 10 CTPOL Output Inverts When CTPOL 1 CTPAU Resume Pause CTM O P Pin CTOC 0 un defined PWM Mode CTDPX 1 Note 1 Here CTDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when CTIO 1 0 00 or 01 4 The CTCCLR bit has no influ...

Page 75: ...ith CCRP and CCRA registers The CCRP is 8 bit wide whose value is compared with the highest 8 bits in the counter while the CCRA is 16 bits and therefore compares with all counter bits The only way of changing the value of the 16 bit counter using the application program is to clear the counter by changing the STON bit from low to high The counter will also be cleared automatically by a counter ov...

Page 76: ...nter operation When in a Pause condition the TM will remain powered up and continue to consume power The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6 4 STCK2 STCK0 Select STM Counter clock 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fTBC 101 fTBC 110 STCK rising edge clock 111 STCK ...

Page 77: ...ctive state 10 PWM output 11 Single pulse output Capture Input Mode 00 Input capture at rising edge of STP 01 Input capture at falling edge of STP 10 Input capture at falling rising edge of STP 11 Input capture disabled Timer counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached The function that these bits select depends u...

Page 78: ... signal is active high or active low Bit 2 STPOL STM Output polarity Control 0 Non invert 1 Invert This bit controls the polarity of the TM output pin When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in the Timer Counter Mode Bit 1 STDPX STM PWM period duty Control 0 CCRP period CCRA duty 1 CCRP duty CCRA period This bi...

Page 79: ...it 7 0 D15 D8 STM CCRA High Byte Register bit 7 bit 0 STM 16 bit CCRA bit 15 bit 8 STMRP Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 STMRP STM CCRP High Byte Register bit 7 bit 0 STM CCRP 8 bit register compared with the STM Counter bit 15 bit 8 Comparator P Match Period 0 65536 STM clocks 1 255 256 1 255 STM clocks Thes...

Page 80: ... the counter will be cleared when a compare match occurs from Comparator A However here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when STCCLR is high no STMPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA can not be set to 0 As the name of the mode suggests after ...

Page 81: ...elect Now STIO 1 0 10 Active High Output Select Output not affected by STMAF flag Remains High until reset by STON bit STCCLR 0 STM 1 0 00 STPAU Resume Stop Time CCRP 0 CCRP 0 STPOL Output Pin Reset to initial value Output inverts when STPOL is high Output controlled by other pin shared function Counter Value Compare Match Output Mode STCCLR 0 Note 1 With STCCLR 0 a Comparator P match will clear t...

Page 82: ... Remains High until reset by STON bit STCCLR 1 STM 1 0 00 STPAU Resume Stop Time CCRA 0 STPOL Output Pin Reset to initial value Output inverts when STPOL is high Output controlled by other pin shared function Counter Value Output does not change No STMAF flag generated on CCRA overflow CCRA 0 Counter overflow STMPF not generated Compare Match Output Mode STCCLR 1 Note 1 With STCCLR 1 a Comparator ...

Page 83: ...f the CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register The PWM waveform frequency and duty cycle can therefore be con...

Page 84: ... Stop If STON bit low Counter reset when STON returns high PWM resumes operation Output controlled by Other pin shared function Time STDPX 0 STM 1 0 10 STPOL Output Inverts When STPOL 1 STPAU Resume Pause STM O P Pin STOC 0 PWM Mode STDPX 0 Note 1 Here STDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues running even when STIO 1 0 00 or 01 4 The S...

Page 85: ...nter Stop If STON bit low Counter reset when STON returns high PWM resumes operation Output controlled by Other pin shared function Time STDPX 1 STM 1 0 10 STPOL Output Inverts When STPOL 1 STPAU Resume Pause STM O P Pin STOC 0 PWM Mode STDPX 1 Note 1 Here STDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when STIO 1 0 00 or 01 4 The STCCL...

Page 86: ... which can be implemented using the application program However in the Single Pulse Mode the STON bit can also be made to automatically change from low to high using the external STCK pin which will in turn initiate the Single Pulse output When the STON bit transitions to a high level the counter will start running and the pulse leading edge will be generated The STON bit should remain high when t...

Page 87: ...0 10 STIO 1 0 11 Pulse Width set by CCRA Output Inverts when STPOL 1 No CCRP Interrupts generated STM O P Pin STOC 0 STCK pin Software Trigger Cleared by CCRA match STCK pin Trigger Auto set by STCK pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Mode Note 1 Counter stopped by CCRA match 2 CCRP is not used 3 The pulse is triggered by setting the STON bit high or ...

Page 88: ...es from low to high which is initiated using the application program When the required edge transition appears on the STP pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated Irrespective of what events occur on the STP pin the counter will continue to free run until the STON bit changes from high to low When a CCRP compare match occurs the coun...

Page 89: ...TIO 1 Value XX YY XX YY Active edge Active edge Active edge Rising edge 1 Falling edge 1 Both edges 11 Disa le Captu e Capture Input Mode Note 1 STM 1 0 01 and active edge set by the STIO 1 0 bits 2 A TM Capture input pin active edge transfers the counter value to CCRA 3 The STCCLR bit is not used 4 No output function STOC and STPOL bits are not used 5 CCRP determines the counter value and the cou...

Page 90: ...nd Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 10 bits wide The only way of changing the value of the 10 counter using the application program is to clear the counter by changing the PTnON bit from low to high The counter will also be cleared automatically by a counter overflow or a compare match with one of its associate...

Page 91: ... Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 PTnPAU PTMn Counter Pause Control 0 Run 1 Pause The counter can be paused by setting this bit high Clearing the bit to zero restores normal counter operation When in a Pause condition the TM will remain powered up and continue to consume power The counter will retain its residual value when this...

Page 92: ...o ensure reliable operation the TM should be switched off before any changes are made to the PTnM1 and PTnM0 bits In the Timer Counter Mode the TM output pin control must be disabled Bit 5 4 PTnIO1 PTnIO0 Select PTPn output function Compare Match Output Mode 00 No change 01 Output low 10 Output high 11 Toggle output PWM Mode Single Pulse Output Mode 00 Force inactive state 01 Force active state 10...

Page 93: ...utput polarity control 0 Non invert 1 Invert This bit controls the polarity of the PTPn output pin When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero It has no effect if the TM is in theTimer Counter Mode Bit 1 PTnCKS Input Capture trigger source selection 0 External Clock source of Capture Input Mode comes from PTPn 1 External Clock source of Capture...

Page 94: ... PTMn 10 bit Counter bit 9 bit 8 PTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 PTMn CCRA Low Byte Register bit 7 bit 0 PTMn 10 bit CCRA bit 7 bit 0 PTMnAH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 PTMn CCRA High Byte Register Bit 1 Bit 0 PTMn 10 b...

Page 95: ...y will both be generated If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A However here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated In the Compare Matc...

Page 96: ...ial Level Low if PTnOC 0 Output Toggle with PTMnAF flag Note PTnIO 1 0 10 Active High Output select Here PTnIO 1 0 11 Toggle Output select Output not affected by PTMnAF flag Remains High until reset by PTnON bit Output Pin Reset to Initial value Output Inverts when PTnPOL is high un defined Compare Match Output Mode PTnCCLR 0 n 0 1 Note 1 With PTnCCLR 0 a Comparator P match will clear the counter ...

Page 97: ... Output select Here PTnIO 1 0 11 Toggle Output select Output not affected by PTMnAF flag Remains High until reset by PTnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTnPOL is high PTMPF not generated No PTMnAF flag generated on CCRA overflow Output does not change Compare Match Output Mode PTnCCLR 1 n 0 1 Note 1 With PTnCCLR 1 a Compar...

Page 98: ...values As both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM mode the PTnCCLR bit has no effect as the PWM period Both of the CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to co...

Page 99: ...p if PTnON bit low Counter Reset when PTnON returns high PTnM 1 0 10 PTnIO 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When PTnPOL 1 PWM Period set by CCRP PTM O P Pin PTnOC 0 PWM mode n 0 1 Note 1 A counter clear sets the PWM Period 2 The internal PWM function continues running even when PTnIO 1 0 00 or 01 3 The PTnCCLR bit...

Page 100: ...put When the PTnON bit transitions to a high level the counter will start running and the pulse leading edge will be generated The PTnON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However ...

Page 101: ...CRA Output Inverts when PTnPOL 1 No CCRP Interrupts generated PTM O P Pin PTnOC 0 PTCKn pin Software Trigger Cleared by CCRA match PTCKn pin Trigger Auto set by PTCKn pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Mode n 0 1 Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse is triggered by the PTCKn pin or by setting the PTnON bit high 4 A PTCKn pin ...

Page 102: ...respective of what events occur on the PTPn or PTCKn pin the counter will continue to free run until the PTnON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a TM interrupt will also be generated Counting the number of ove...

Page 103: ...top PTnIO 1 Value Active edge Active edge Active edge Rising edge 1 Falling edge 1 Both edges 11 Disa le Captu e XX YY XX YY Capture Input Mode n 0 1 Note 1 PTnM 1 0 01 and active edge set by the PTnIO 1 0 bits 2 A TM Capture input pin active edge transfers the counter value to CCRA 3 PTnCCLR bit not used 4 No output function PTnOC and PTnPOL bits are not used 5 CCRP determines the counter value a...

Page 104: ...nals such as that from sensors or other control signals and convert these signals directly into a 12 bit digital value The accompanying block diagram shows the overall internal structure of the A D converter together with its associated registers A D Converter Structure A D Converter Register Description Overall operation of the A D converter is controlled using five registers A read only register...

Page 105: ...ons such as the selection of which analog channel is connected to the internal A D converter the digitised data format the A D clock source as well as controlling the start function and monitoring the A D converter end of conversion status The ACS4 in the ADCR1 register and ACS2 ACS0 bits in the ADCR0 register define the ADC input channel number As the device contains only one actual analog to dig...

Page 106: ...able the A D converter If the bit is set high then the A D converter will be switched off reducing the device power consumption As the A D converter will consume a limited amount of power even when not executing a conversion this may be an important consideration in power sensitive battery powered applications Note 1 it is recommended to set ADOFF 1 before entering IDLE SLEEP Mode for saving power...

Page 107: ... LVR function is disabled then the bandgap reference circuit will be automatically switched off to conserve power When VBG is switched on for use by the A D converter a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A D conversion Bit 5 4 Unimplemented read as 0 Bit 3 VREFS Selecte ADC reference voltage 0 Internal ADC power AVDD 1 VREF pin This bit is used t...

Page 108: ...rought from low to high but not low again the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset It is the START bit that is used to control the overall start operation of the internal analog to digital converter The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete This bit will be automatica...

Page 109: ...6μs 32μs 64μs Undefined 2MHz 500ns 1μs 2μs 4μs 8μs 16μs 32μs Undefined 4MHz 250ns 500ns 1μs 2μs 4μs 8μs 16μs Undefined 8MHz 125ns 250ns 500ns 1μs 2μs 4μs 8μs Undefined 12MHz 83ns 167ns 333ns 667ns 1 33μs 2 67μs 5 33μs Undefined 16MHz 62ns 125ns 250ns 500ns 1μs 2μs 4μs Undefined A D Clock Period Examples Controlling the power on off function of the A D converter circuitry is implemented using the A...

Page 110: ...r will be overridden The A D converter has its own reference voltage pins VREF however the reference voltage can also be supplied from the power supply pin a choice which is made through the VREFS bit in the ADCR1 register A D Input Structure Summary of A D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A D conversion process Step 1 ...

Page 111: ...p above can be omitted The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing After an A D conversion process has been initiated by the application program the microcontroller internal hardware will begin to carry out the conversion during which time the program can continue with other functions The time taken for...

Page 112: ...nsfer Function As the device contains a 12 bit A D converter its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the AVDD or VREF voltage this gives a single bit analog input value of AVDD or VREF divided by 4096 1 LSB AVDD or VREF 4096 The A D Converter input voltage value can be calculated using the following equation A D input voltage A ...

Page 113: ...le ADC interrupt mov a 03H mov ADCR1 a select fSYS 8 as A D clock and switch off VBG clr ADOFF mov a 0Fh setup ACERL to configure pins AN0 AN3 mov ACERL a mov a 00h mov ADCR0 a enable and connect AN0 channel to A D converter start_conversion clr START high pulse on start bit to initiate conversion set START reset A D clr START start A D polling_EOC sz EOCB poll the ADCR0 register EOCB bit to detec...

Page 114: ...ion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interrupt ADC interrupt service routine ADC_ISR mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a ADRL read low byte conversion result value mov adrl_buffer a save result to user defined regist...

Page 115: ...ugh the SPI interface specification can control multiple slave devices from a single master but the device provides only one SCS pin If the master needs to control multiple slave devices from a single master the master can use I O pin to select the slave devices SPI Interface Operation The SPI interface is a full duplex synchronous serial data link It is a four line interface with pin names SDI SD...

Page 116: ...M0 SIMDBNC1 SIMDBNC0 SIMEN SPIICF SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIM Registers List The SIMD register is used to store the data being transmitted and received The same register is used by both the SPI and I2 C functions Before the devices write data to the SPI bus the actual data to be transmitted must be placed in the SIMD register After the data is receive...

Page 117: ...g if the I2 C or SPI function they are used to control the SPI Master Slave selection and the SPI Master clock frequency The SPI clock is a function of the system clock but can also be chosen to be sourced from the CTM If the SPI Slave Mode is selected then the clock will be supplied by an external Master device Bit 4 Unimplemented read as 0 Bit 3 2 SIMDBNC1 SIMDBNC0 I2 C Debounce Time Selection 0...

Page 118: ... low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated The CKPOLB bit determines the base condition of the clock line if the bit is high then the SCK line will be low when t...

Page 119: ...mplete the TRF flag will be set automatically but must be cleared using the application program In the Slave Mode when the clock signal from the master has been received any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register The master should output a SCS signal to enable the slave device before a clock signal is provided The slave data...

Page 120: ...Rev 1 21 120 November 09 2017 HT66F488 HT66F489 A D Flash MCU with EEPROM SPI Slave Mode Timing CKEG 1 SPI Transfer Control Flowchart ...

Page 121: ...se outputs Note that no chip select line exists as each device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C bus When two devices communicate with each other on the bidirectional I2 C bus one is known as the master device and one as the slave device Both master and slave can transmit and receive data however it is the master device that has ov...

Page 122: ... SRW RCIN RXAK SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 SIMTOC SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2 C Register List SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 SIMDBNC1 SIMDBNC0 SIMEN SPIICF R W R W R W R W R W R W R W R W POR 1 1 1 0 0 0 0 Bit 7 5 SIM2 SIM0 SIM Operating Mode Control 000 SPI master mode SPI clock is fSY...

Page 123: ...rred The SPIICF bit is determined by SCS pin When SCS pin is set to 1 it will clear the SPI counter Meanwhile the interrupt is occurred if slave device didn t complete data received then the incompleted flag SPIICF is set to 1 SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R W R R R R W R W R R W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF I2 C Bus data transfer completion flag 0...

Page 124: ...e application program after wake up This bit should be set to 1 to enable the I2 C address match wake up from the SLEEP or IDLE Mode If the IAMWU bit has been set before entering the SLEEP or IDLE mode to enable the I2 C address match wake up then this bit must be cleared by the application program after wake up to ensure correction device operation Bit 0 RXAK I2 C Bus Receive acknowledge flag 0 S...

Page 125: ...s also used by the SPI interface but has the name SIMC2 The SIMA register is the location where the 7 bit slave address of the slave device is stored Bits 7 1 of the SIMA register define the device slave address Bit 0 is not defined When a master device which is connected to the I2 C bus sends out an address which matches the slave address in the SIMA register the slave device will be selected Not...

Page 126: ...slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8 bit data transfer During a data transfer note that after the 7 bit slave address has been transmitted the following bit which is the 8th bit is the read write bit whose value will be placed in the SRW bit This bit will be checked by t...

Page 127: ...tion of a data byte transfer When a slave address is matched the device must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line I2 C Bus Read Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2 C bus or wr...

Page 128: ...ta will be stored in the SIMD register If setup as a transmitter the slave device must first write the data to be transmitted into the SIMD register If setup as a receiver the slave device must read the transmitted data from the SIMD register When the slave receiver receives the data byte it must generate an acknowledge bit known as TXAK on the 9th clock The slave device which is setup as a transm...

Page 129: ...e I2 C bus is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts to count on an I2 C bus START address match condition and is cleared by an SCL falling edge Before the next SCL falling edge arrives if the time elapsed is greater than the time out period specified by the SIMTOC register then a time out condition w...

Page 130: ...nd the registers will be reset into the following condition Register After I2 C Time out SIMD SIMA SIMC0 No change SIMC1 Reset to POR condition I2 C Registers after Time out The SIMTOF flag can be cleared by the application program There are 64 time out period selections which can be selected using the SIMTOS bits in the SIMTOC register The time out duration is calculated by the formula 1 64 32 fS...

Page 131: ...interrupt on address detect last character bit 1 Transmitter and receiver enabled independently 2 byte Deep FIFO Receive Data Buffer Transmit and receive interrupts Transmit and Receive Multiple Interrupt Generation Sources Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect RX pin Wake up UART External Interface To communicate with an external serial interface th...

Page 132: ...Data Memory the Receiver Shift Register is not mapped and is therefore inaccessible to the application program It should be noted that the actual register for data transmission and reception although referred to in the text and in application programs as separate TXR and RXR registers only exists as a single shared register in the Data Memory This shared register known as the TXR RXR register is u...

Page 133: ...followed by an access to the RXR data register Bit 5 FERR Framing error flag 0 No framing error is detected 1 Framing error is detected The FERR flag is the framing error flag When this read only flag is 0 it indicates that there is no framing error When the flag is 1 it indicates that a framing error has been detected for the current character The flag can also be cleared by a software sequence w...

Page 134: ...ter or a break is queued and ready to be sent Bit 0 TXIF Transmit TXR data register status 0 Character is not transferred to the transmit shift register 1 Character has transferred to the transmit shift register TXR data register is empty The TXIF flag is the transmit data register empty flag When this read only flag is 0 it indicates that the character is not transferred to the transmitter shift ...

Page 135: ...e most significant bit position with a parity bit Bit 4 PRT Parity type selection bit 0 Even parity for parity generator 1 Odd parity for parity generator This bit is the parity type selection bit When this bit is equal to 1 odd parity type will be selected If the bit is equal to 0 then even parity type will be selected Bit 3 STOPS Number of Stop bits selection 0 One stop bit format is used 1 Two ...

Page 136: ... be disabled with any pending data receptions being aborted In addition the receive buffers will be reset In this situation the RX pin will be used as an I O or other pin shared functional pin If the RXEN bit is equal to 1 and the UARTEN bit is also equal to 1 the receiver will be enabled and the RX pin will be controlled by the UART Clearing the RXEN bit during a reception will cause the data rec...

Page 137: ... the transmitter idle interrupt If this bit is equal to 1 and when the transmitter idle flag TIDLE is set due to a transmitter idle condition the UART interrupt request flag will be set If this bit is equal to 0 the UART interrupt request flag will not be influenced by the condition of the TIDLE flag Bit 0 TEIE Transmitter Empty interrupt enable control 0 Transmitter empty interrupt is disabled 1 ...

Page 138: ... rate is determined using a discrete value N placed in the BRG register there will be an error associated between the actual and requested value The following example shows how the BRG register value N and the error value can be calculated Calculating the register and error values For a clock frequency of 4MHz and with BRGH set to 0 determine the BRG register value N the actual baud rate and the e...

Page 139: ...LSB first Although the UART transmitter and receiver are functionally independent they both use the same data format and baud rate In all cases stop bits will be used for data transmission Enabling disabling the UART The basic on off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register If the UARTEN TXEN and RXEN bits are set then these two UART pins will ...

Page 140: ... case the 9th bit which is the MSB needs to be stored in the TX8 bit in the UCR1 register At the transmitter core lies the Transmitter Shift Register more commonly known as the TSR whose data is obtained from the transmit data register which is known as the TXR register The data to be transmitted is loaded into this TXR register by the application program The TSR register is not written to with ne...

Page 141: ...l generate an interrupt During a data transmission a write instruction to the TXR register will place the data into the TXR register which will be copied to the shift register at the end of the present transmission When there is no data transmission in progress a write instruction to the TXR register will place the data directly into the shift register resulting in the commencement of data transmi...

Page 142: ...ead mode the RXR register forms a buffer between the internal bus and the receiver shift register The RXR register is a two byte deep FIFO data buffer where two bytes can be held in the FIFO while a third byte can continue to be received Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in otherwise this third byte will b...

Page 143: ...lags will possibly be set Idle status When the receiver is reading data which means it will be in between the detection of a start bit and the reading of a stop bit the receiver status flag in the USR register otherwise known as the RIDLE flag will have a zero value In between the reception of a stop bit and the detection of the next start bit the RIDLE flag will have a high value which indicates ...

Page 144: ...nditions are created if its corresponding interrupt control is enabled and the stack is not full the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set Th...

Page 145: ...terrupt will only be generated if the highest received bit has a high value Note that the MFE URE and EMI interrupt enable bits must also be enabled for correct interrupt generation This highest address bit is the 9th bit if BNO 1 or the 8th bit if BNO 0 If this bit is high then the received word will be defined as an address rather than data A Data Available interrupt will be generated every time...

Page 146: ... as it takes certain system clock cycles after a wake up before normal microcontroller resumes the UART interrupt will not be generated until after this time has elapsed Interrupts Interrupts are an important part of any microcontroller system When an external event or an internal function such as a Timer Module or an A D converter requires microcontroller attention their corresponding interrupt w...

Page 147: ...C2 ADF MF2F MF1F MF0F ADE MF2E MF1E MF0E INTC3 SIMF DEF TB1F TB0F SIME DEE TB1E TB0E MFI0 CTMAF CTMPF CTMAE CTMPE MFI1 LVF STMAF STMPF LVE STMAE STMPE MFI2 PTM1AF PTM1PF PTM0AF PTM0PF PTM1AE PTM1PE PTM0AE PTM0PE Interrupt Register Contents INTEG0 Register Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6...

Page 148: ...NT4S0 Defines INT4 interrupt active edge 00 Disabled Interrupt 01 Rising Edge Interrupt 10 Falling Edge Interrupt 11 Dual Edge Interrupt INTC0 Register Bit 7 6 5 4 3 2 1 0 Name INT2F INT1F INT0F INT2E INT1E INT0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 INT2F INT2 Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 Interrupt Req...

Page 149: ...request 1 Interrupt request Bit 6 INT5F INT5 Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 INT4F INT4 Interrupt Request Flag 0 No request 1 Interrupt request Bit 4 INT3F INT3 Interrupt Request Flag 0 No request 1 Interrupt request Bit 3 UARE UART Interrupt Control 0 Disable 1 Enable Bit 2 INT5E INT5 Interrupt Control 0 Disable 1 Enable Bit 1 INT4E INT4 Interrupt Control 0 Disable 1...

Page 150: ...F Multi function 2 Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 MF1F Multi function 1 Interrupt Request Flag 0 No request 1 Interrupt request Bit 4 MF0F Multi function 0 Interrupt Request Flag 0 No request 1 Interrupt request Bit 3 ADE A D Converter Interrupt Control 0 Disable 1 Enable Bit 2 MF2E Multi function 2 Interrupt Control 0 Disable 1 Enable Bit 1 MF1E Multi function 1 Int...

Page 151: ...equest Bit 6 DEF Data EEPROM Interrupt Request Flag 0 No request 1 Interrupt request Bit 5 TB1F Time Base 1 Interrupt Request Flag 0 No request 1 Interrupt request Bit 4 TB0F Time Base 0 Interrupt Request Flag 0 No request 1 Interrupt request Bit 3 SIME Serial Interface Module Interrupt Control 0 Disable 1 Enable Bit 2 DEE Data EEPROM Interrupt Control 0 Disable 1 Enable Bit 1 TB1E Time Base 1 Int...

Page 152: ...t 0 CTMPE CTM Comparator P match interrupt control 0 Disable 1 Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name LVF STMAF STMPF LVE STMAE STMPE R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 LVF LVD interrupt request flag 0 No request 1 Interrupt request Bit 6 Unimplemented read as 0 Bit 5 STMAF STM Comparator A match interrupt request flag 0 No request 1 Interrupt request Bit 4 STMPF STM Comparat...

Page 153: ...r P match interrupt request flag 0 No request 1 Interrupt request Bit 5 PTM0AF PTM0 Comparator A match interrupt request flag 0 No request 1 Interrupt request Bit 4 PTM0PF PTM0 Comparator P match interrupt request flag 0 No request 1 Interrupt request Bit 3 PTM1AE PTM1 Comparator A match interrupt control 0 Disable 1 Enable Bit2 PTM1PE PTM1 Comparator P match interrupt control 0 Disable 1 Enable B...

Page 154: ...minated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable bits together with their associated request flags are shown in the accompanying diagrams with their order of priority Some interrupt sources have their own individual vector wh...

Page 155: ...the program to branch to the interrupt vector address the global interrupt enable bit EMI and the external interrupt enable bit INTnE must first be set Additionally the correct interrupt edge type must be selected using the INTEGn register to enable the external interrupt function and to choose the trigger edge type As the external interrupt pin is pin shared with an I O pin it can only be configu...

Page 156: ...uest flag ADF is set which occurs when the A D conversion process finishes To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and A D Interrupt enable bit ADE must first be set When the interrupt is enabled the stack is not full and the A D conversion process has ended a subroutine call to the A D Converter Interrupt vector will take place...

Page 157: ...X fSYS 4 fTBC fTB 212 215 TB11 TB10 TBCK bit LXT M U X Configuration Option Time Base 0 Interrupt 28 215 TB02 TB00 Time Base Interrupt Serial Interface Module Interrupts A SIM Interrupt request will take place when the SIM Interrupt request flag SIMF is set which occurs when a byte of data has been received or transmitted by the SIM interface To allow the program to branch to its respective interr...

Page 158: ...flags will not be automatically cleared they have to be cleared by the application program LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi function Interrupt An LVD Interrupt request will take place when the LVD Interrupt request flag LVF is set which occurs when the Low Voltage Detector function detects a low power supply voltage To allow the program to branch to it...

Page 159: ...service routine is executed as only the Multi function interrupt request flags MF0F MF2F will be automatically cleared the individual request flag for the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately ...

Page 160: ...in function selection This enables the LCD COM and SEG driver to generate the necessary VSS 1 3 VDD 2 3 VDD voltage and VDD levels for LCD 1 3 bias operation The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin shared function selection bits Note that the Port Control register does no...

Page 161: ...A 11 100μA Bit 4 LCDEN SCOM and SSEG module on off control 0 Off 1 On SCOMn and SSEGm can be enable by COMnEN and SEGmEN if LCDEN 1 If LCDEN 0 SCOMn and SSEGm output VSS When LCDEN is set it will turn on the DC path of resistor to generate LCD Bias voltage Bit 3 COM3EN LCD or other function selection 0 Other function 1 SCOM3 SSEG3 Bit 2 COM2EN LCD or other function selection 0 Other function 1 SCO...

Page 162: ...0 Bit 7 COM5EN LCD or other function selection 0 Other function 1 SCOM5 SSEG5 Bit 6 COM4EN LCD or other function selection 0 Other function 1 SCOM4 SSEG4 Bit 5 COMSEGS5 SCOM5 or SSEG 5 selection 0 SCOM5 1 SSEG5 Bit 4 COMSEGS4 SCOM4 or SSEG 4 selection 0 SCOM4 1 SSEG4 Bit 3 COMSEGS3 SCOM3 or SSEG 3 selection 0 SCOM3 1 SSEG3 Bit 2 COMSEGS2 SCOM2 or SSEG 2 selection 0 SCOM2 1 SSEG2 Bit 1 COMSEGS1 SCO...

Page 163: ...EG13EN SSEG13 function control 0 Disable 1 Enable Bit 6 SEG12EN SSEG12 function control 0 Disable 1 Enable Bit 5 SEG11EN SSEG11 function control 0 Disable 1 Enable Bit 4 SEG10EN SSEG10 function control 0 Disable 1 Enable Bit 3 SEG9EN SSEG9 function control 0 Disable 1 Enable Bit 2 SEG8EN SSEG8 function control 0 Disable 1 Enable Bit 1 SEG7EN SSEG7 function control 0 Disable 1 Enable Bit 0 SEG6EN S...

Page 164: ...le 1 Enable Bit 5 SEG19EN SSEG19 function control 0 Disable 1 Enable Bit 4 SEG18EN SSEG18 function control 0 Disable 1 Enable Bit 3 SEG17EN SSEG17 function control 0 Disable 1 Enable Bit 2 SEG16EN SSEG16 function control 0 Disable 1 Enable Bit 1 SEG15EN SSEG15 function control 0 Disable 1 Enable Bit 0 SEG14EN SSEG14 function control 0 Disable 1 Enable Note SSEG14 SSEG15 share the pins with OSC1 XT...

Page 165: ...t 4 SEG26EN SSEG26 function control 0 Disable 1 Enable Bit 3 SEG25EN SSEG25 function control 0 Disable 1 Enable Bit 2 SEG24EN SSEG24 function control 0 Disable 1 Enable Bit 1 SEG23EN SSEG23 function control 0 Disable 1 Enable Bit 0 SEG22EN SSEG22 function control 0 Disable 1 Enable LCD waveform The accompanying waveform diagram shows a typical 1 3 Bias LCD waveform generated using the application ...

Page 166: ...Vbias value of 2 3VDD SEG_H In frame 1 the COM signal output can have a value of VSS or have a Vbias value of 2 3VDD SEG_H The SEG signal can have a value of VDD have a Vbias value of 1 3VDD SEG_L The SCOM0 SCOMn waveform is controlled by the application program using the FRAME bit and the corresponding I O data register for the respective SCOM pin to determine whether the SCOM0 SCOMn output has a...

Page 167: ...termined A low voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector circuits A...

Page 168: ... fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi function interrupts providing an alternative means of low voltage detection in addition to polling the LVDO bit The interrupt will only be generated after a delay of tLVD after the LVDO bit has ...

Page 169: ...options are selected using the HT IDE software development tools As these options are programmed into the device using the hardware programming tools once they are selected they cannot be changed later using the application program All options must be defined for proper system function the details of which are shown in the table No Options Oscillator Option 1 High Speed Low Speed System Oscillator...

Page 170: ...le to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one cyc...

Page 171: ...ch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of...

Page 172: ...ith Carry result in Data Memory 1Note Z C AC OV SC CZ DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Mem...

Page 173: ...ne RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None ITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL m Increment table pointer TBLP first and Read table ...

Page 174: ...result in Data Memory 2Note C Logic Operation LAND A m Logical AND Data Memory to ACC 2 Z LOR A m Logical OR Data Memory to ACC 2 Z LXOR A m Logical XOR Data Memory to ACC 2 Z LANDM A m Logical AND ACC to Data Memory 2Note Z LORM A m Logical OR ACC to Data Memory 2Note Z LXORM A m Logical XOR ACC to Data Memory 2Note Z LCPL m Complement Data Memory 2Note Z LCPLA m Complement Data Memory with resul...

Page 175: ...h result in ACC 2Note None Table Read LTABRD m Read table to TBLH and Data Memory 3Note None LTABRDL m Read table last page to TBLH and Data Memory 3Note None LITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL m Increment table pointer TBLP first and Read table last page to TBLH and Data Memory 3Note None Miscellaneous LCLR m Clear Data Memory 2...

Page 176: ...ulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C SC ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC AND A m Logical AND Data Memory to ACC Descripti...

Page 177: ... previously contained a 1 are changed to 0 and vice versa Operation m m Affected flag s Z CPLA m Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented 1 s complement Bits which previously contained a 1 are changed to 0 and vice versa The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchan...

Page 178: ...eration m m 1 Affected flag s Z INCA m Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1 The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC m 1 Affected flag s Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address Program exe...

Page 179: ...flag s Z RET Return from subroutine Description The Program Counter is restored from the stack Program execution continues at the restored address Operation Program Counter Stack Affected flag s None RET A x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data Program execution ...

Page 180: ...es the Carry bit and the original carry flag is rotated into the bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 C C m 7 Affected flag s C RR m Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7 Operation m i m i 1 i 0 6 m...

Page 181: ... ACC m C Affected flag s OV Z AC C SC CZ SBCM A m Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Data Memory Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positi...

Page 182: ...tion while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m 1 Skip if ACC 0 Affected flag s None SNZ m i Skip if Data Memory is not 0 Description If the specified Data Memory is not 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instru...

Page 183: ...emory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetc...

Page 184: ...peration m program code low byte TBLH program code high byte Affected flag s None ITABRDL m Increment table pointer low byte first and read table last page to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operat...

Page 185: ...tored in the Accumulator Operation ACC ACC m Affected flag s OV Z AC C SC LADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC LAND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perfor...

Page 186: ...f the high nibble is greater than 9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition ...

Page 187: ...ry are rotated left by 1 bit with bit 7 rotated into bit 0 Operation m i 1 m i i 0 6 m 0 m 7 Affected flag s None LRLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0...

Page 188: ...ified Data Memory and the carry flag are rotated right by 1 bit Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 C C m 0 Affected flag s C LSBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data...

Page 189: ...t i of the specified Data Memory is set to 1 Operation m i 1 Affected flag s None LSIZ m Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is ...

Page 190: ...e set to 1 Operation m ACC m Affected flag s OV Z AC C SC CZ LSWAP m Swap nibbles of Data Memory Description The low order and high order nibbles of the specified Data Memory are interchanged Operation m 3 m 0 m 7 m 4 Affected flag s None LSWAPA m Swap nibbles of Data Memory with result in ACC Description The low order and high order nibbles of the specified Data Memory are interchanged The result...

Page 191: ...ected flag s None LITABRD m Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the program code addressed by the table pointer TBHP and TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None LITABRDL m Inc...

Page 192: ...r intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Materi...

Page 193: ...ensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 705 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 17 9 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 194: ...imensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 9 9 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 195: ...used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reser...

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