Rev. 1.00
162
September 11, 2018
Rev. 1.00
163
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
•
Make the correct selection of BNO, PRT and PREN bits to define the word length, parity type.
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Setup the BRG register to select the desired baud rate.
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Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin.
At this point the receiver will be enabled which will begin to look for a start bit.
When a character is received the following sequence of events will occur:
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The RXIF bit in the USR register will be set when the TXR_RXR register has data available.
There will be at most one more character available before an overrun error occurs.
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When the contents of the shift register have been transferred to the TXR_RXR register, then if
the RIE bit is set, an interrupt will be generated.
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If during reception, a frame error, noise error, parity error, or an overrun error has been detected,
then the error flags can be set.
The RXIF bit can be cleared using the following software sequence:
1. A USR register access
2. A TXR_RXR register read execution
Receive Break
Any break character received by the UART will be managed as a framing error. The receiver will
count and expect a certain number of bit times as specified by the values programmed into the BNO
bit plus one stop bit. If the break is much longer than 13 bit times, the reception will be considered
as complete after the number of bit times specified by BNO plus one stop bit. The RXIF bit is set,
FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate
and the RIDLE bit is set. A break is regarded as a character that contains only zeros with the FERR
flag set. If a long break signal has been detected, the receiver will regard it as a data frame including
a start bit, data bits and the invalid stop bit and the FERR flag will be set. The receiver must wait for
a valid stop bit before looking for the next start bit. The receiver will not make the assumption that
the break condition on the line is the next start bit. The break character will be loaded into the buffer
and no further data will be received until stop bits are received. It should be noted that the RIDLE
read only flag will go high when the stop bits have not yet been received. The reception of a break
character on the UART registers will result in the following:
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The framing error flag, FERR, will be set.
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The receive data register, TXR_RXR, will be cleared.
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The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.
Idle Status
When the receiver is reading data, which means it will be in between the detection of a start bit and
the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE
flag, will have a zero value. In between the reception of a stop bit and the detection of the next start
bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition.
Receiver Interrupt
The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the
receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift
Register, RSR, to the Receive Data Register, TXR_RXR. An overrun error can also generate an
interrupt if RIE=1.
