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Rev. 1.00

124

September 11, 2018

Rev. 1.00

125

September 11, 2018

HT45F4050

A/D NFC Flash MCU

HT45F4050

A/D NFC Flash MCU

A/D Conversion Rate and Timing Diagram

A complete A/D conversion contains two parts, data sampling and data conversion. The data
sampling which is defined as t

ADS

takes 4 A/D conversion clock cycles and the data conversion takes

12 A/D converter clock cycles. Therefore a total of 16 A/D conversion clock cycles for an A/D
conversion which is defined as t

ADC

are necessary.

Maximum single A/D conversion rate=A/D conversion clock period /16

The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for the
A/D conversion is 16t

ADCK

clock cycles where t

ADCK

is equal to the A/D conversion clock period.

ADCEN

START

ADBZ

SACS[3:0]

off

on

off

on

t

ON2ST

t

ADS

A/D sampling time

t

ADS

A/D sampling time

Start of A/D conversion

Start of A/D conversion

Start of A/D conversion

End of A/D

conversion

End of A/D

conversion

t

ADC

A/D conversion time

t

ADC

A/D conversion time

t

ADC

A/D conversion time

0011B

0010B

0000B

0001B

A/D channel switch

(SAINS[3:0]=0000B)

A/D Conversion Timing – External Channel Input

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Summary of Contents for HT45F4050

Page 1: ...A D NFC Flash MCU HT45F4050 Revision V1 00 Date September 11 2018 ...

Page 2: ...ics 24 Software Controlled LCD Driver Electrical Characteristics 25 Power on Reset Characteristics 25 System Architecture 25 Clocking and Pipelining 26 Program Counter 26 Stack 27 Arithmetic and Logic Unit ALU 27 Flash Program Memory 28 Structure 28 Special Vectors 28 Look up Table 29 Table Program Example 29 In Circuit Programming ICP 30 On Chip Debug Support OCDS 31 Data Memory 31 Structure 32 D...

Page 3: ...or LXT 44 Internal 32kHz Oscillator LIRC 45 Operating Modes and System Clocks 45 System Clocks 45 System Operation Modes 46 Control Register 47 Operating Mode Switching 50 Standby Current Considerations 54 Wake up 54 Watchdog Timer 55 Watchdog Timer Clock Source 55 Watchdog Timer Control Register 55 Watchdog Timer Operation 56 Reset and Initialisation 57 Reset Functions 57 Reset Initial Conditions...

Page 4: ...view 118 A D Converter Register Description 119 A D Converter Reference Voltage 122 A D Converter Input Signals 123 A D Converter Operation 124 A D Conversion Rate and Timing Diagram 125 Summary of A D Conversion Steps 126 Programming Considerations 127 A D Conversion Function 127 A D Converter Programming Examples 128 Comparator 130 Comparator Operation 130 Comparator Registers 130 Input Offset C...

Page 5: ...D Converter Interrupt 198 Time Base Interrupts 198 Serial Interface Module Interrupt 200 UART Transfer Interrupt 200 NFC Interrupt 201 EEPROM Write Interrupt 201 LVD Interrupt 201 TM Interrupts 201 Interrupt Wake up Function 202 Programming Considerations 202 Low Voltage Detector LVD 203 LVD Register 203 LVD Operation 204 Configuration Options 205 Application Descriptions 206 NFC Operating Princip...

Page 6: ...5F4050 A D NFC Flash MCU Instruction Set Summary 211 Table Conventions 211 Extended Instruction Set 213 Instruction Definition 215 Extended Instruction Definition 224 Package Information 231 48 pin LQFP 7mm 7mm Outline Dimensions 232 ...

Page 7: ...three instruction cycles Table read instructions 115 powerful instructions 8 level subroutine nesting Bit manipulation instruction Peripheral Features Flash Program Memory 8K 16 RAM Data Memory 256 8 True EEPROM Memory 64 8 Watchdog Timer function 41 bidirectional I O lines I O source current programmable Software controlled 4 SCOM lines LCD driver with 1 2 bias Two external interrupt lines shared...

Page 8: ...nd UART interface functions popular interfaces which provide designers with a means of easy communication with external peripheral hardware Protective features such as an internal Watchdog Timer Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments A full choice of external...

Page 9: ... Port F Driver PF0 PF7 VDD AVDD VDD AVDD VSS AVSS VSS AVSS RES Pin Shared With Port B Clock System HXT LXT XT2 XT1 Pin Shared With Port F OSC2 OSC1 Pin Shared With Port B MUX Pin Shared Node LA LB NFC State Machine NFC Memory ASK 100 Demodulator Limiter Modulator Clock Recovery Field Detector Regulator VDD NFC Peripheral VSSN Pin Shared With Port C D F AN0 AN12 VREF Analog Peripherals 12 bit ADC A...

Page 10: ...ol bits 2 The actual device and its equivalent OCDS EV device share the same package type however the OCDS EV device part number is HT45V4050 Pins OCDSCK and OCDSDA which are pin shared with PA2 and PA0 are only used for the OCDS EV device Pin Description With the exception of the power pins all pins on the device can be referenced by its Port name e g PA0 PA1 etc which refer to the digital I O fu...

Page 11: ...ata line PA5 SCK SCL PA5 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull high and wake up SCK PAS1 IFS0 ST CMOS SPI serial Clock SCL PAS1 IFS0 ST NMOS I2 C clock line PA6 INT0 RX PA6 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull high and wake up INT0 PAS1 INTEG INTC0 IFS1 ST External Interrupt 0 RX PAS1 ST UART RX serial data input PA7 INT1 TX PA7 PAPU PAWU PAS1...

Page 12: ...gh OSC2 PBS1 HXT HXT oscillator pin PC0 AN0 VREFI PC0 PCPU PCS0 ST CMOS General purpose I O Register enabled pull high AN0 PCS0 AN A D Converter analog input VREFI PCS0 AN A D Converter PGA input PC1 AN1 CX VREF PC1 PCPU PCS0 ST CMOS General purpose I O Register enabled pull high AN1 PCS0 AN A D Converter analog input CX PCS0 CMOS Comparator output VREF PCS0 AN A D Converter reference voltage inpu...

Page 13: ...S0 AN A D Converter analog input PD3 AN11 PD3 PDPU PDS0 ST CMOS General purpose I O Register enabled pull high AN11 PDS0 AN A D Converter analog input PE0 STCK STPB PE0 PEPU PES0 ST CMOS General purpose I O Register enabled pull high STCK PES0 IFS0 ST STM clock input STPB PES0 CMOS STM inverted output PE1 STPI STP PE1 PEPU PES0 ST CMOS General purpose I O Register enabled pull high STPI PES0 IFS0 ...

Page 14: ...l high XT2 PFS1 LXT LXT oscillator pin PF5 XT1 PF5 PFPU PFS1 ST CMOS General purpose I O Register enabled pull high XT1 PFS1 LXT LXT oscillator pin PF6 AN12 C PF6 PFPU PFS1 ST CMOS General purpose I O Register enabled pull high AN12 PFS1 AN A D Converter analog input C PFS1 AN Comparator negative input PF7 C PF7 PFPU PFS1 ST CMOS General purpose I O Register enabled pull high C PFS1 AN Comparator ...

Page 15: ...z 1 8 5 5 V fSYS fHXT 8MHz 2 0 5 5 fSYS fHXT 12MHz 2 7 5 5 fSYS fHXT 16MHz 3 3 5 5 Operating Voltage HIRC fSYS fHIRC 4MHz 1 8 5 5 V fSYS fHIRC 8MHz 2 0 5 5 fSYS fHIRC 12MHz 2 7 5 5 Operating Voltage LXT fSYS fLXT 32 768kHz 1 8 5 5 V Operating Voltage LIRC fSYS fLIRC 32kHz 1 8 5 5 V VDDIO VDDIO Pin Power Supply 1 8 VDD V IDD Operating Current HXT 3V No load all peripherals off fSYS fHXT 4MHz 0 8 1 ...

Page 16: ...ad all peripherals off fSYS fH 2 0 5 1 0 mA 5V 1 0 2 0 3V No load all peripherals off fSYS fH 64 0 25 0 5 5V 0 5 1 0 Operating Current fH 12MHz HXT 3V No load all peripherals off fSYS fH 2 0 7 1 4 mA 5V 1 4 2 8 3V No load all peripherals off fSYS fH 64 0 35 0 7 5V 0 7 1 4 ISTB Standby Current SLEEP mode 3V No load all peripherals off WDT off 0 2 0 8 μA 5V 0 5 1 0 3V No load all peripherals off WDT...

Page 17: ...64 IOH Source Current for I O Ports 3V VOH 0 9VDD SLEDCn m 1 m 00B n 0 1 or 2 m 0 2 4 or 6 1 0 2 0 mA 5V 2 0 4 0 3V VOH 0 9VDDIO VDDIO VDD SLEDCn m 1 m 00B n 0 1 or 2 m 0 2 4 or 6 1 0 2 0 5V 2 0 4 0 3V VOH 0 9VDD SLEDCn m 1 m 01B n 0 1 or 2 m 0 2 or or 6 1 75 3 5 5V 3 5 7 0 3V VOH 0 9VDDIO VDDIO VDD SLEDCn m 1 m 01B n 0 1 or 2 m 0 2 4 or 6 1 75 3 5 5V 3 5 7 0 3V VOH 0 9VDD SLEDCn m 1 m 10B n 0 1 o...

Page 18: ... 12 3 3V 5 5V fSYS fHXT 16MHz 16 System Clock HIRC 1 8V 5 5V fSYS fHIRC 4MHz 4 MHz 2 0V 5 5V fSYS fHIRC 8MHz 8 2 7V 5 5V fSYS fHIRC 12MHz 12 System Clock LXT 1 8V 5 5V fSYS fLXT 32 768kHz 32 768 kHz System Clock LIRC 1 8V 5 5V fSYS fLIRC 32kHz 32 kHz fHIRC High Speed Internal RC Oscillator HIRC 4MHz trim 4MHz VDD 3V 3 0V Ta 25 C 2 4 2 MHz 2 2V 5 5V Ta 25 C 5 4 5 3 0V Ta 0 C 70 C 5 4 5 3 0V Ta 40 C...

Page 19: ... 25 C 20 12 20 High Speed Internal RC Oscillator HIRC 12MHz trim 12MHz VDD 5V 5 0V Ta 25 C 2 12 2 MHz 4 0V 5 5V Ta 25 C 5 12 5 5 0V Ta 0 C 70 C 5 12 5 5 0V Ta 40 C 85 C 5 12 5 4 0V 5 5V Ta 0 C 70 C 7 12 7 4 0V 5 5V Ta 40 C 85 C 10 12 10 5 0V Ta 25 C 20 4 20 5 0V Ta 25 C 20 8 20 fLIRC Low Speed Internal RC Oscillator LIRC 2 2V 5 5V Ta 25 C 5 32 5 kHz Ta 40 C 85 C 10 32 10 tTCK CTCK STCK and PTCK Pi...

Page 20: ...d WDT Time out Hardware Cold Reset 0 tH NFC Function fPLL NFC PLL Frequency 2 2V 5 5V Ta 40 C 85 C 7 13 56 7 MHz tSETUP NFC PLL Setup Time 2 2V 5 5V Ta 40 C 85 C 90 μs tRCY NFC EEPROM Read Time 2 2V 5 5V Ta 40 C 85 C 200 tSYS tWCY NFC EEPROM Write Time 2 2V 5 5V Ta 40 C 85 C 4 6 ms Note tSYS 1 fSYS Memory Characteristics Ta 40 C 85 C unless otherwise specified Symbol Parameter Test Conditions Min ...

Page 21: ... Nonlinearity 1 8V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 2 0μs 4 4 LSB 2V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 0 5μs 3V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 0 5μs 5V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 0 5μs 1 8V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 10μs 3V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 10μs 5V SAINS 3 0 0000B SAVRS 1 0 01B VREF VDD tADCK 10μs...

Page 22: ...unless otherwise specified Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage 2 2 5 5 V VBGREF Bandgap Reference Voltage Ta 40 C 85 C 2 1 2 2 V IBGREF Operating Current 5 5V Ta 40 C 85 C 25 40 μA PSRR Power Supply Rejection Ratio VRIPPLE 1VP P fRIPPLE 100Hz 75 dB En Output Noise no load current f 0 1Hz 10Hz 300 μVRMS ISD Shutdown Current VBGREN 0 0 1 μA tSTART S...

Page 23: ...t 1 8V 5 1 8 5 V LVD enable voltage select 2 0V 5 2 0 5 LVD enable voltage select 2 4V 5 2 4 5 LVD enable voltage select 2 7V 5 2 7 5 LVD enable voltage select 3 0V 5 3 0 5 LVD enable voltage select 3 3V 5 3 3 5 LVD enable voltage select 3 6V 5 3 6 5 LVD enable voltage select 4 0V 5 4 0 5 ILVRLVDBG Operating Current 3V LVD enable LVR enable VLVR 1 9V VLVD 2V 10 μA 5V 8 15 tLVDS LVDO Stable Time Fo...

Page 24: ... Mode Voltage Range 1 8V VSS 0 3 VDD 1 0 V 3V VSS VDD 1 0 5V VSS VDD 1 0 AOL Open Loop Gain 1 8V CNVT 1 0 00B 60 dB 3V 60 5V 60 80 VHYS Hysteresis 1 8V CNVT 1 0 00B 10 30 mV 3V 10 30 5V 10 24 30 tRP Response Time 2 1 8V With 100mV overdrive CLOAD 50pF CNVT 1 0 00B 40 μs 3V 40 μs 5V 40 μs 1 8V With 100mV overdrive CLOAD 50pF CNVT 1 0 01B 3 μs 3V 3 μs 5V 3 μs 1 8V With 100mV overdrive CLOAD 50pF CNV...

Page 25: ...cture The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions r...

Page 26: ... cycles are required to complete instruction execution An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Execute Inst 1 Fetch Inst 2 1 MOV A 12H 2 CALL DELAY 3 CPL 12H 4 5 6 DE...

Page 27: ...fter a device reset the Stack Pointer will point to the top of the stack If the stack is full and an enabled interrupt takes place the interrupt request flag will be recorded but the acknowledge signal will be inhibited When the Stack Pointer is decremented by RET or RETI the interrupt will be serviced This feature prevents stack overflow allowing the programmer to use the structure more easily Ho...

Page 28: ...using the appropriate programming tools the Flash device offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating Structure The Program Memory has a capacity of 8K 16 bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be ...

Page 29: ...table data is defined and retrieved from the microcontroller This example uses raw table data located in the Program Memory which is stored there using the ORG statement The value at this ORG statement is 1F00H which refers to the start address of the last page within the 8K words Program Memory The table pointer low byte register is setup here to have an initial value of 06H This will ensure that...

Page 30: ...eir programs on the same device As an additional convenience Holtek has provided a means of programming the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later stage This enables product manufactur...

Page 31: ... chip However the two OCDS pins which are pin shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP For a more detailed OCDS description refer to the corresponding document named Holtek e Link for 8 bit MCU OCDS User s Guide Holtek e Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On chip Debug Support Data Address input output OCDSCK OCDSCK On chip ...

Page 32: ...dress in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space For the accessed data memory which is located in any data memory sectors except sector 0 the extended instructions can be used to access the data memory instead...

Page 33: ...L 5BH SADOH 5CH SADC0 5DH SADC1 5EH SADC2 5FH SIMC0 60H SIMC1 61H SIMD 62H SIMC2 SIMA 63H 64H SIMTOC SCOMC 65H USR 66H UCR1 67H 68H UCR2 69H TXR_RXR 6AH BRG 6BH 6CH 6DH IFS0 6EH IFS1 6FH 70H PAS0 PAS1 PBS0 71H 72H 73H PBS1 PCS0 PCS1 PDS0 PES0 PES1 74H 75H 76H 77H 78H 79H 7AH PFS0 PFS1 7BH 00H 01H 02H 03H IAR0 MP0 IAR1 MP1L MP1H 04H ACC 05H PCL 06H TBLP 07H TBLH 08H TBHP 09H STATUS 0AH 0BH IAR2 0CH...

Page 34: ...tly will result in no operation Memory Pointers MP0 MP1L MP1H MP2L MP2H Five Memory Pointers known as MP0 MP1L MP1H MP2L and MP2H are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers i...

Page 35: ...ry pointer MP1L sdz block check if last memory location has been cleared jmp loop continue The important point to note here is that in the example shown above no reference is made to specific Data Memory addresses Direct Addressing Program Example using extended instructions data section data temp db code section at 0 code org 00h start lmov a m move m data to acc lsub a m 1 compare m and m 1 data...

Page 36: ...ted Their value can be changed for example using the INC or DEC instructions allowing for easy table data pointing and reading TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed Note that the lower order table data byte is transferred to a user defined location Status Register STATUS This 8 bit register contains the zero...

Page 37: ...perational result of different flags for different instuctions For SUB SUBM LSUB LSUBM instructions the CZ flag is equal to the Z flag For SBC SBCM LSBC LSBCM instructions the CZ flag is the AND operation result which is performed by the previous operation CZ flag and current operation zero flag For other instructions the CZ flag willl not be affected Bit 5 TO Watchdog Time Out flag 0 After power ...

Page 38: ...in Sector 0 and a single control register in Sector 1 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control register EEC As both the EEA and EED registers are located in Sector 0 they can be directly accessed in the same way as any other Special Function Register The EEC regist...

Page 39: ...out Clearing this bit to zero will inhibit Data EEPROM read operations Bit 0 RD EEPROM Read Control 0 Read cycle has finished 1 Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle This bit will be automatically reset to zero by the hardware after the read cycle has finished Setting this bit high will have no effect ...

Page 40: ...ore poll the WR bit to determine when the write cycle has ended Write Protection Protection against inadvertent write operation is provided in several ways After the device is powered on the Write Enable bit in the control register will be cleared preventing any write operations Also at power on the Memory Pointer high byte register MP1H or MP2H will be reset to zero which means that Data Memory S...

Page 41: ...ode until the EEPROM read or write operation is totally completed Otherwise the EEPROM read or write operation will fail Programming Examples Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer low byte MP1L MOV MP1L A MP1L points to EEC register MOV A 01H setup Memory Pointer high byte MP1H MOV MP1H A SET IAR1 1 set RDEN bi...

Page 42: ...the performance power ratio a feature especially important in power sensitive portable applications Type Name Freq Pins External High Speed Crystal HXT 400kHz 16MHz OSC1 OSC2 Internal High Speed RC HIRC 4 8 12MHz External Low Speed Crystal LXT 32 768kHz XT1 XT2 Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are four methods of generating the system clock two hi...

Page 43: ...rs However for some crystal types and frequencies to ensure oscillation it may be necessary to add two small value capacitors C1 and C2 Using a ceramic resonator will usually require two small value capacitors C1 and C2 to be connected as shown for oscillation to occur The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer s specification For oscillat...

Page 44: ...frequency compensation due to different crystal manufacturing tolerances After the LXT oscillator is enabled by setting the LXTEN bit to 1 there is a time delay associated with the LXT oscillator waiting for it to start up When the microcontroller enters the SLEEP or IDLE Mode the system clock is switched off to stop microcontroller activity and to conserve power However in many microcontroller ap...

Page 45: ...that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks required for high performance will by their nature increase current consumption and of course vice versa lower speed clocks reduce current consumption As Holtek has provided the device with both high and low speed clock sources and the means to sw...

Page 46: ...nt modes of operation for the microcontroller each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application There are two modes allowing normal operation of the microcontroller the NORMAL Mode and SLOW Mode The remaining four modes the SLEEP IDLE0 IDLE1 and IDLE2 Mode are used when the microcontroller CPU is sw...

Page 47: ...ck can still continue to operate if the WDT function is enabled by the WDTC register IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions IDLE1 Mode The...

Page 48: ...s bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an HALT instruction Bit 0 FSIDEN Low Frequency oscillator control when CPU is switched off 0 Disable 1 Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an HALT instruction HIRCC Register Bit...

Page 49: ...OSC1 and OSC2 pins are enabled and the HXTEN bit is set to 1 to enable the HXT oscillator it is invalid to change the value of this bit Otherwise this bit value can be changed with no operation on the HXT function Bit 1 HXTF HXT oscillator stable flag 0 HXT unstable 1 HXT stable This bit is used to indicate whether the HXT oscillator is stable or not When the HXTEN bit is set to 1 to enable the HX...

Page 50: ...g the CKS2 CKS0 bits in the SCC register while Mode Switching from the NORMAL SLOW Modes to the SLEEP IDLE Modes is executed via the HALT instruction When an HALT instruction is executed whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register NORMAL fSYS fH fH 64 fH on CPU run fSYS on fSUB on SLOW fSYS fSUB fSUB on ...

Page 51: ...Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs NORMAL Mode SLOW Mode CKS2 CKS0 111 SLEEP Mode FHIDEN 0 FSIDEN 0 HALT instru...

Page 52: ...DEN 0 FSIDEN 1 HALT instruction is executed IDLE1 Mode FHIDEN 1 FSIDEN 1 HALT instruction is executed IDLE2 Mode FHIDEN 1 FSIDEN 0 HALT instruction is executed Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the HALT instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to 0 In this mode all...

Page 53: ...truction is executed under the conditions described above the following will occur The fH and fSUB clocks will be on but the application program will stop at the HALT instruction The Data Memory contents and registers will maintain their present condition The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and WDT timeout flag TO will be ...

Page 54: ...on to resume After the system enters the SLEEP or IDLE Mode it can be woken up from one of various sources listed as follows An external falling edge on Port A An external reset A system interrupt A WDT overflow If the system is woken up by an external reset the device will experience a full system reset however if the device is woken up by a WDT overflow a Watchdog Timer reset will be initiated A...

Page 55: ...peration of the Watchdog Timer WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function software control 10101 Disable 01010 Enable Other values Reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller the reset operation will be activated afte...

Page 56: ...reset the device after a delay time tSRESET After power on these bits will have the value of 01010B WE4 WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable Disable Control Under normal program operation a Watchdog Timer time out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a Watchdog ...

Page 57: ...ain threshold Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All types of reset operations result in different register conditions being setup Reset Functions There are several ways in which a microcontroller reset can occur through events occurring both internally and externally Power on Reset The most fundamental and unavoidable reset is the one that oc...

Page 58: ... is added in environments where power line noise is significant External RES Circuit Pulling the RES Pin low using external hardware will also execute a device reset In this case as in the case of other resets the Program Counter will reset to zero and program execution initiated from this point Internal Reset tRSTD tSST 0 9VDD 0 4VDD RES RESReset Timing Chart There is an internal reset control re...

Page 59: ...on Bit 1 LRF LVR control register software reset flag Refer to the Low Voltage Reset section Bit 0 WRF WDT control register software reset flag Refer to the Watchdog Timer Control Register section Low Voltage Reset LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device The LVR function is always enabled with a specific LVR voltage VLVR If ...

Page 60: ...alues above will also result in the generation of an MCU reset The reset operation will be activated after a delay time tSRESET However in this situation the register contents will be reset to the POR value RSTFC Register Bit 7 6 5 4 3 2 1 0 Name RSTF LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 4 Unimplemented read as 0 Bit 3 RSTF Reset control register software reset flag Refer t...

Page 61: ...operations such as the SLEEP or IDLE Mode function or Watchdog Timer The reset flags are shown in the table TO PDF Reset Conditions 0 0 Power on reset u u RESor LVR reset during Normal or SLOW Mode operation 1 u WDT time out reset during Normal or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation Note u stands for unchanged The following table indicates the way in whic...

Page 62: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u INTC3 0 0 0 0 0 0 0 0 u u PA 1111 1111 1111 1111 1111 1111 1111 1111 u u u u u u u u PAC 1111 1111 1111 1111 1111 1111 1111 1111 u u u u u u u u PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PB 1111...

Page 63: ...0 0 0 u u u u u PTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PTMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PTMDH 0 0 0 0 0 0 0 0 u u PTMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PTMAH 0 0 0 0 0 0 0 0 u u PTMRPL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u...

Page 64: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PBS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PBS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PCS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PCS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PDS0...

Page 65: ... instruction MOV A m where m denotes the port address For output operation all the data is latched and remains unchanged until the output latch is rewritten Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 P...

Page 66: ... actual available bits for each I O Port may be different LVPUC Register Bit 7 6 5 4 3 2 1 0 Name LVPU R W R W POR 0 Bit 7 1 Unimplemented read as 0 Bit 0 LVPU Low Voltage pull high resistor control 0 All pin pull high resistors are 30kΩ 5V 1 All pin pull high resistors are 7 5kΩ 5V Note that as the pull high resistors are formed using long PMOS transistors lower operating voltages will result in ...

Page 67: ...ill be used to read the output register However it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin PxC Register Bit 7 6 5 4 3 2 1 0 Name PxC7 PxC6 PxC5 PxC4 PxC3 PxC2 PxC1 PxC0 R W R W R W R W R W R W R W R W R W POR 1 1 1 1 1 1 1 1 PxCn I O Port x Pin type selection 0 Output 1 Input The PxCn bit is used ...

Page 68: ...rrent Level 2 11 Source current Level 3 max Bit 1 0 SLEDC01 SLEDC00 PA3 PA0 source current selection 00 Source current Level 0 min 01 Source current Level 1 10 Source current Level 2 11 Source current Level 3 max SLEDC1 Register Bit 7 6 5 4 3 2 1 0 Name SLEDC15 SLEDC14 SLEDC13 SLEDC12 SLEDC11 SLEDC10 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 4 SLEDC15 SLEDC1...

Page 69: ...DC20 PE3 PE0 source current selection 00 Source current Level 0 min 01 Source current Level 1 10 Source current Level 2 11 Source current Level 3 max I O Port Power Source Control This device supports different I O port power source selections for PA1 and PA3 PA7 The port power can come from either the power pin VDD or VDDIO which is determined using the PMPS1 PMPS0 bits in the PMPS register The V...

Page 70: ...e selected The most important point to note is to make sure that the desired pin shared function is properly selected and also deselected For most pin shared functions to select the desired pin shared function the pin shared function should first be correctly selected using the corresponding pin shared control register After that the corresponding peripheral functional setting should be configured...

Page 71: ...n 00 PA1 INT0 01 PA1 INT0 10 PA1 INT0 11 SCS Bit 1 0 PAS01 PAS00 PA0 pin shared function selection 00 PA0 01 PA0 10 PA0 11 PA0 PAS1 Register Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PAS17 PAS16 PA7 pin shared function selection 00 PA7 INT1 01 PA7 INT1 10 PA7 INT1 11 TX Bit 5 4 PAS15 PAS14 PA6 pin shared...

Page 72: ...ion 00 PB1 PTPI 01 PB1 PTPI 10 PB1 PTPI 11 PTP Bit 1 0 PBS01 PBS00 PB0 pin shared function selection 00 PB0 01 PB0 10 PB0 11 CX PBS1 Register Bit 7 6 5 4 3 2 1 0 Name PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PBS17 PBS16 PB7 pin shared function selection 00 PB7 01 PB7 10 PB7 11 OSC2 Bit 5 4 PBS15 PBS14 PB6 pin shared function se...

Page 73: ...function selection 00 PC1 01 CX 10 VREF 11 AN1 Bit 1 0 PCS01 PCS00 PC0 pin shared function selection 00 PC0 01 PC0 10 VREFI 11 AN0 PCS1 Register Bit 7 6 5 4 3 2 1 0 Name PCS17 PCS16 PCS15 PCS14 PCS13 PCS12 PCS11 PCS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PCS17 PCS16 PC7 pin shared function selection 00 PC7 STCK 01 PC7 STCK 10 STPB 11 AN7 Bit 5 4 PCS15 PCS14 PC6 pin share...

Page 74: ...PD1 01 PD1 10 PD1 11 AN9 Bit 1 0 PDS01 PDS00 PD0 pin shared function selection 00 PD0 01 PD0 10 PD0 11 AN8 PES0 Register Bit 7 6 5 4 3 2 1 0 Name PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PES07 PES06 PE3 pin shared function selection 00 PE3 01 PE3 10 VDDIO 11 CTP Bit 5 4 PES05 PES04 PE2 pin shared function selection 00 PE2 CTCK ...

Page 75: ...ared function selection 00 PF3 01 PF3 10 SCK SCL 11 SCOM3 Bit 5 4 PFS05 PFS04 PF2 pin shared function selection 00 PF2 01 PF2 10 SDI SDA 11 SCOM2 Bit 3 2 PFS03 PFS02 PF1 pin shared function selection 00 PF1 01 PF1 10 SDO 11 SCOM1 Bit 1 0 PFS01 PFS00 PF0 pin shared function selection 00 PF0 01 PF0 10 SCS 11 SCOM0 PFS1 Register Bit 7 6 5 4 3 2 1 0 Name PFS17 PFS16 PFS15 PFS14 PFS13 PFS12 PFS11 PFS10...

Page 76: ...PF0 Bit 6 SDISDAPS SDI SDA input source pin selection 0 PA4 1 PF2 Bit 5 SCKSCLPS SCK SCL input source pin selection 0 PA5 1 PF3 Bit 4 STPIPS STPI input source pin selection 0 PC6 1 PE1 Bit 3 PTPIPS PTPI input source pin selection 0 PC2 1 PB1 Bit 2 STCKPS STCK input source pin selection 0 PC7 1 PE0 Bit 1 CTCKPS CTCK input source pin selection 0 PB4 1 PE2 Bit 0 PTCKPS PTCK input source pin selection...

Page 77: ...ut state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the port control registers PAC PFC are then programmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers PA PF are first programmed Selecting which pins are inputs and which are outputs can be achiev...

Page 78: ...els 1 1 1 Single Pulse Output 1 1 PWM Alignment Edge Edge Edge PWM Adjustment Period Duty Duty or Period Duty or Period Duty or Period TM Function Summary TM Operation The different types of TM offer a diverse range of functions from simple timing operations to PWM signal generation The key to understanding how the TM operates is to see it in terms of a free running count up counter whose value is...

Page 79: ... or PTMC1 register respectively There is another capture input PTCK for PTM capture input mode which can be used as the external trigger input source except the PTPI pin The TMs each have two output pins xTP and xTPB The xTPB is the inverted signal of the xTP output When the TM is in the Compare Match Output Mode these pins can be controlled by the TM to switch to a high or low level or to toggle ...

Page 80: ... the CCRA and CCRP low byte registers named xTMAL and PTMRPL using the following access procedures Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values Data Bus 8 bit Buffer xTMDH xTMDL xTMAH xTMAL xTM Counter Register Read only xTM CCRA Register Read Write PTMRPH PTMRPL PTM CCRP Register Read Write The following steps show the...

Page 81: ...CCRA is 16 bit wide and therefore compares with all counter bits The only way of changing the value of the 16 bit counter using the application program is to clear the counter by changing the CTON bit from low to high The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators When these conditions occur a CTM interrupt signal will...

Page 82: ... Off control 0 Off 1 On This bit controls the overall on off function of the CTM Setting the bit high enables the counter to run while clearing the bit disables the CTM Clearing this bit to zero will stop the counter from counting and turn off the CTM which will reduce its power consumption When the bit changes state from low to high the internal counter value will be reset to zero however when th...

Page 83: ...el of the CTON bit from low to high In the PWM Output Mode the CTIO1 and CTIO0 bits determine how the CTM output pin changes state when a certain compare match condition occurs The PWM output function is modified by changing these two bits It is necessary to only change the values of the CTIO1 and CTIO0 bits only after the CTM has been switched off Unpredictable PWM outputs will occur if the CTIO1...

Page 84: ...the CCRP bits are all cleared to zero The CTCCLR bit is not used in the PWM Output Mode CTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 CTM Counter Low Byte Register bit 7 bit 0 CTM 16 bit Counter bit 7 bit 0 CTMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 CTM Count...

Page 85: ... there are two ways in which the counter can be cleared One is when a compare match occurs from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both CTMAF and CTMPF interrupt request flags for the Comparator A and Comparator P respectively will both be generated If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when...

Page 86: ... 0 Output Toggle with CTMAF flag Note CTIO 1 0 10 Active High Output select Here CTIO 1 0 11 Toggle Output select Output not affected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high Compare Match Output Mode CTCCLR 0 Note 1 With CTCCLR 0 a Comparator P match will clear the counter ...

Page 87: ...ffected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high CTMPF not generated No CTMAF flag generated on CCRA overflow Output does not change CTCCLR 1 CTM 1 0 00 CCRA Int flag CTMAF CCRP Int flag CTMPF Compare Match Output Mode CTCCLR 1 Note 1 With CTCCLR 1 a Comparator A match will ...

Page 88: ... the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registe...

Page 89: ...ycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRP CTM O P Pin CTOC 0 CCRA Int flag CTMAF CCRP Int flag CTMPF CTDPX 0 CTM 1 0 10 PWM Output Mode CTDPX 0 Note 1 Here CTDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when CTIO 1 0 00 or 01 4 The CTCCLR ...

Page 90: ... Reset when CTON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRA CTM O P Pin CTOC 0 CTDPX 1 CTM 1 0 10 PWM Output Mode CTDPX 1 Note 1 Here CTDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when CTIO 1 0 00 or 01 4 The CTCCLR ...

Page 91: ...th highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all counter bits The only way of changing the value of the 16 bit counter using the application program is to clear the counter by changing the STON bit from low to high The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators When these c...

Page 92: ...it controls the overall on off function of the STM Setting the bit high enables the counter to run while clearing the bit disables the STM Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption When the bit changes state from low to high the internal counter value will be reset to zero however when the bit changes from high to low...

Page 93: ...a compare match occurs After the STM output pin changes state it can be reset to its initial level by changing the level of the STON bit from low to high In the PWM Output Mode the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs The PWM output function is modified by changing these two bits It is necessary to only change the values ...

Page 94: ... counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero The STCCLR bit is not used in the PWM Output Mode Single Pulse Output Mode or Capture Input Mode STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 STM Counter Low Byte Register bit 7 bit 0 STM 16 bit Counter bit 7 bit 0 STMDH Registe...

Page 95: ...ere are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively will both be generated If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare mat...

Page 96: ... 0 Output Toggle with STMAF flag Note STIO 1 0 10 Active High Output select Here STIO 1 0 11 Toggle Output select Output not affected by STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when STPOL is high Compare Match Output Mode STCCLR 0 Note 1 With STCCLR 0 a Comparator P match will clear the counter ...

Page 97: ...ut select Here STIO 1 0 11 Toggle Output select Output not affected by STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when STPOL is high STMPF not generated No STMAF flag generated on CCRA overflow Output does not change Compare Match Output Mode STCCLR 1 Note 1 With STCCLR 1 a Comparator A match will ...

Page 98: ...RP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the va...

Page 99: ... Reset when STON returns high STDPX 0 STM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when STPOL 1 PWM Period set by CCRP STM O P Pin STOC 0 PWM Output Mode STDPX 0 Note 1 Here STDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when STIO 1 0 00 or 01 4 The STCCLR ...

Page 100: ...r Reset when STON returns high STDPX 1 STM 1 0 10 PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when STPOL 1 PWM Period set by CCRA STM O P Pin STOC 0 PWM Output Mode STDPX 1 Note 1 Here STDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when STIO 1 0 00 or 01 4 The STCCLR...

Page 101: ... edge will be generated The STON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the STON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single...

Page 102: ...t Inverts when STPOL 1 No CCRP Interrupts generated STM O P Pin STOC 0 STCK pin Software Trigger Cleared by CCRA match STCK pin Trigger Auto set by STCK pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Output Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the STCK pin or by setting the STON bit high 4 A STCK pin active edge will au...

Page 103: ...resent value in the counter will be latched into the CCRA registers and a STM interrupt generated Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match...

Page 104: ...1 0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 STM 1 0 01 and active edge set by the STIO 1 0 bits 2 A STM Capture input pin active edge transfers the counter value to CCRA 3 STCCLR bit not used 4 No output function STOC and STPOL bits are not used 5 CCRP determines the counter value and the counte...

Page 105: ...nd CCRA registers The CCRP and CCRA comparators are 10 bit wide whose value is compared with all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changing the PTON bit from low to high The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators When these...

Page 106: ...t controls the overall on off function of the PTM Setting the bit high enables the counter to run while clearing the bit disables the PTM Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption When the bit changes state from low to high the internal counter value will be reset to zero however when the bit changes from high to low ...

Page 107: ...put pin when a compare match occurs After the PTM output pin changes state it can be reset to its initial level by changing the level of the PTON bit from low to high In the PWM Output Mode the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a certain compare match condition occurs The PTM output function is modified by changing these two bits It is necessary to only chang...

Page 108: ...hod can only be implemented if the CCRP bits are all cleared to zero The PTCCLR bit is not used in the PWM Output Single Pulse Output or Capture Input Mode PTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 PTM Counter Low Byte Register bit 7 bit 0 PTM 10 bit Counter bit 7 bit 0 PTMDH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R R...

Page 109: ...mparator A and Comparator P respectively will both be generated If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A However here only the PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when PTCCLR is high no PTMPF interrupt request flag wil...

Page 110: ...h PTMAF flag Note PTIO 1 0 10 Active High Output select Here PTIO 1 0 11 Toggle Output select Output not affected by PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTPOL is high PTCCLR 0 PTM 1 0 00 Compare Match Output Mode PTCCLR 0 Note 1 With PTCCLR 0 a Comparator P match will clear the counter ...

Page 111: ... 1 0 11 Toggle Output select Output not affected by PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTPOL is high PTMPF not generated No PTMAF flag generated on CCRA overflow Output does not change PTCCLR 1 PTM 1 0 00 Compare Match Output Mode PTCCLR 1 Note 1 With PTCCLR 1 a Comparator A match will...

Page 112: ...h the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM Output Mode the PTCCLR bit has no effect as the PWM period Both of the CCRP and CCRA registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control t...

Page 113: ... Counter Reset when PTON returns high PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When PTPOL 1 PWM Period set by CCRP PTM O P Pin PTOC 0 PTM 1 0 10 PWM Output Mode Note 1 The counter is cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when PTIO 1 0 00 or 01 4 The PTCCLR bit ha...

Page 114: ... leading edge will be generated The PTON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the PTON bit and thus generate th...

Page 115: ...No CCRP Interrupts generated PTM O P Pin PTOC 0 PTCK pin Software Trigger Cleared by CCRA match PTCK pin Trigger Auto set by PTCK pin Software Trigger Software Clear Software Trigger Software Trigger PTM 1 0 10 PTIO 1 0 11 Single Pulse Output Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the PTCK pin or by setting the PTON bit high 4 A PTCK pin active edge will au...

Page 116: ...respective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a PTM interrupt will also be generated Counting the number of over...

Page 117: ...TIO 1 0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 PTM 1 0 01 and active edge set by the PTIO 1 0 bits 2 A PTM Capture input pin active edge transfers the counter value to CCRA 3 PTCCLR bit not used 4 No output function PTOC and PTPOL bits are not used 5 CCRP determines the counter value and the co...

Page 118: ...l value The external or internal analog signal to be converted is determined by the SAINS and SACS bit fields Note that when the internal analog signal is to be converted using the SAINS bit field the external channel analog input will be automatically be switched off More detailed information about the A D converter input signal is described in the A D Converter Control Registers and A D Converte...

Page 119: ...ter as shown in the accompanying table D0 D11 are the A D conversion result data bits Any unused bits will be read as zero Note that the A D converter data register contents will keep unchanged if the A D converter is disabled ADRFS SADOH SADOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A D Converter Data Register...

Page 120: ... be cleared to zero after the A D conversion is complete Bit 5 ADCEN A D Converter function enable control 0 Disable 1 Enable This bit controls the A D converter internal function This bit should be set high to enable the A D converter If the bit is set low then the A D converter will be switched off reducing the device power consumption When the A D converter function is disabled the contents of ...

Page 121: ...off regardless of the SACS bit field value It will prevent the external channel input from being connected together with the internal analog signal Bit 3 Unimplemented read as 0 Bit 2 0 SACKS2 SACKS0 A D conversion clock source selection 000 fSYS 001 fSYS 2 010 fSYS 4 011 fSYS 8 100 fSYS 16 101 fSYS 32 110 fSYS 64 111 fSYS 128 SADC2 Register Bit 7 6 5 4 3 2 1 0 Name ADPGAEN PGAIS SAVRS1 SAVRS0 PGA...

Page 122: ...nal reference source supplied on pin VREF or an internal reference source derived from the PGA output VR The desired selection is made using the SAVRS1 SAVRS0 bits in the SADC2 register The internal reference voltage is amplified through a programmable gain amplifier PGA which is controlled by the ADPGAEN bit in the SADC2 register The PGA gain can be equal to 1 1 667 2 5 or 3 333 selected using th...

Page 123: ...l converter hardware circuit each of the external and internal analog signals must be routed to the converter The SAINS3 SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the external channel input or internal analog signal The SACS3 SACS0 bits in the SADC0 register are used to determine which external channel input is selected to be converte...

Page 124: ...version clock source speed that can be selected As the recommended value of permissible A D conversion clock period tADCK is from 0 5μs to 10μs care must be taken for system clock frequencies For example if the system clock operates at a frequency of 4MHz the SACKS2 SACKS0 bits should not be set to 000 110 or 111 Doing so will give A D conversion clock periods that are less than the minimum A D co...

Page 125: ...to digital conversion process and its associated timing After an A D conversion process has been initiated by the application program the microcontroller internal hardware will begin to carry out the conversion during which time the program can continue with other functions The time taken for the A D conversion is 16tADCK clock cycles where tADCK is equal to the A D conversion clock period ADCEN S...

Page 126: ... analog signal is selected to be converted the external channel analog input will automatically be disconnected Then go to Step 6 Step 6 Select the reference voltage source by configuring the SAVRS1 SAVRS0 bits in the SADC2 register Enable the PGA select the PGA input signal and the desired PGA gain if the PGA output voltage or its division is selected as the A D converter reference voltage Step 7...

Page 127: ...al A D converter reference voltage VREF this gives a single bit analog input value of VREF divided by 4096 1 LSB VREF 4096 The A D Converter input voltage value can be calculated using the following equation A D converter input voltage A D converter output digital value VREF 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A D...

Page 128: ...nd A D input signal comes from external channel mov SADC1 a mov a 00H select AVDD as A D reference voltage source mov SADC2 a mov a 03h setup PCS0 to configure pin AN0 mov PCS0 a mov a 20h enable A D converter and select AN0 external channel input mov SADC0 a start_conversion clr START high pulse on start bit to initiate conversion set START reset A D converter clr START start A D conversion polli...

Page 129: ...T bit to initiate conversion set START reset A D converter clr START start A D conversion clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interrupt ADC interrupt service routine ADC_ISR mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a SADOL read low byte conversion result value mov S...

Page 130: ...mparator inputs approach their switching level some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals This can be minimised by the hysteresis function which will apply a small amount of positive feedback to the comparator When the comparator operates in the normal mode the hysteresis function will automatically be enable...

Page 131: ... comparator output bit The polarity of this bit is determined by the voltages on the comparator inputs and by the condition of the CPOL bit Bit 3 2 CNVT1 CNVT0 Comparator response time selection 00 Response time 0 max 01 Response time 1 10 Response time 2 11 Response time 3 min These bits are used to select the comparator response time The detailed response time specifications are listed in the Co...

Page 132: ...tep 1 Set COFM 1 to enable the comparator input offset calibration mode and set the CRSP bit to select the reference input Step 2 Set COF 4 0 00000B and read the CMPO bit Step 3 Increase the COF 4 0 value by 1 and then read the CMPO bit If the CMPO bit state does not change then repeat Step 3 until the CMPO bit state changes If the CMPO bit state changes record the COF field value as VOS1 and then...

Page 133: ...tion protocol simplifying the programming requirements when communicating with external hardware devices The communication is full duplex and operates as a slave master type where the device can be either master or slave Although the SPI interface specification can control multiple slave devices from a single master but the device provides only one SCS pin If the master needs to control multiple s...

Page 134: ...nd upon the condition of certain control bits such as CSEN and SIMEN SIMD TX RX Shift Register SDI Pin Clock Edge Polarity Control CKEG CKPOLB Clock Source Select fSYS fSUB PTM CCRP match frequency 2 SCK Pin CSEN Busy Status SDO Pin SCS Pin Data Bus WCOL TRF SIMICF SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface These are ...

Page 135: ...requency The SIMC2 register is used for other control functions such as LSB MSB selection write collision flag etc SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 SIMDEB1 SIMDEB0 SIMEN SIMICF R W R W R W R W R W R W R W R W POR 1 1 1 0 0 0 0 Bit 7 5 SIM2 SIM0 SIM operating mode control 000 SPI master mode SPI clock is fSYS 4 001 SPI master mode SPI clock is fSYS 16 010 SPI master mode SPI c...

Page 136: ...t will be set to 1 together with the TRF bit When this condition occurs the corresponding interrupt will occur if the interrupt function is enabled However the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 D7 D6 Und...

Page 137: ...bit is the Transmit Receive Complete flag and is set 1 automatically when an SPI data transmission is completed but must set to 0 by the application program It can be used to generate an interrupt SPI Communication After the SPI interface is enabled by setting the SIMEN bit high then in the Master Mode when data is written to the SIMD register transmission reception will begin simultaneously When ...

Page 138: ...D2 D5 D1 D6 D0 D7 SPI Master Mode Timing SCK CKPOLB 1 SCK CKPOLB 0 SCS SDO SDI Data Capture Write to SIMD SDO does not change until first SCK edge D7 D0 D6 D1 D5 D2 D4 D3 D3 D4 D2 D5 D1 D6 D0 D7 SPI Slave Mode Timing CKEG 0 SCK CKPOLB 1 SCK CKPOLB 0 SCS SDO SDI Data Capture D7 D0 D6 D1 D5 D2 D4 D3 D3 D4 D2 D5 D1 D6 D0 D7 Write to SIMD SDO changes as soon as writing occurs SDO is floating if SCS 1 ...

Page 139: ...Data into SIMD WCOL 1 Transmission completed TRF 1 Read Data from SIMD Clear TRF END Transfer finished A SPI Transfer Master or Slave SIMEN 1 Configure CKPOLB CKEG CSEN and MLS A SIM 2 0 000 001 010 011 or 100 SIM 2 0 101 Master Slave Y Y N N N Y SPI Transfer Control Flowchart ...

Page 140: ...LB in the SIMC2 register If in Slave Mode the SCK line will be in a floating condition If the SIMEN bit is low then the bus will be disabled and SCS SDI SDO and SCK will all become I O pins or the other functions using the corresponding pin shared control bits In the Master Mode the Master will always generate the clock signal The clock and data transmission will be initiated after data has been w...

Page 141: ... data transferred in on the SDI line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SIMD register Step 5 Check the WCOL bit if set high then a collision error has occurred so return to step 4 If equal to zero then go to the following step Step 6 Check the TRF bit or wait for an SIM SPI serial bus interrupt Step 7 Read data from the...

Page 142: ...ch device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C bus When two devices communicate with each other on the bidirectional I2 C bus one is known as the master device and one as the slave device Both master and slave can transmit and receive data however it is the master device that has overall control of the bus For the device which only op...

Page 143: ... Standard Mode 100kHz I2 C Fast Mode 400kHz No Debounce fSYS 2 MHz fSYS 5 MHz 2 system clock debounce fSYS 4 MHz fSYS 10 MHz 4 system clock debounce fSYS 8 MHz fSYS 20 MHz I2 C Minimum fSYS Frequency Requirements I2 C Registers There are three control registers associated with the I2 C bus SIMC0 SIMC1 and SIMTOC one address register SIMA and one data register SIMD Register Name Bit 7 6 5 4 3 2 1 0...

Page 144: ...There are three control registers for the I2 C interface SIMC0 SIMC1 and SIMTOC The SIMC0 register is used to control the enable disable function and to set the data transmission clock frequency The SIMC1 register contains the relevant flags which are used to indicate the I2 C communication status Another register SIMTOC is used to control the I2 C time out function and is described in the corresp...

Page 145: ...lised by the application program while the relevant I2 C flags such as HCF HAAS HBB SRW and RXAK will be set to their default states Bit 0 SIMICF SIM SPI incomplete flag This bit is only available when the SIM is configured to operate in an SPI slave mode Refer to the SPI register section SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R W R R R R W R W R R W R POR 1 0...

Page 146: ...ansmit mode When the SRW flag is zero the master will write data to the bus therefore the slave device should be in receive mode to read this data Bit 1 IAMWU I2 C address match wake up control 0 Disable 1 Enable This bit should be set to 1 to enable the I2 C address match wake up from the SLEEP or IDLE Mode If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the ...

Page 147: ...completion of an 8 bit data transfer completion or from the I2 C bus time out occurrence During a data transfer note that after the 7 bit slave address has been transmitted the following bit which is the 8th bit is the read write bit whose value will be placed in the SRW bit This bit will be checked by the slave device to determine whether to go into transmit or receive mode Before any transfer of...

Page 148: ...byte transfer or from the I2 C bus time out occurrence When a slave address is matched the device must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line I2 C Bus Read Write Signal The SRW bit in the SIMC1 register defines whether the master device wishes to read d...

Page 149: ...eceiver the slave device must read the transmitted data from the SIMD register When the slave receiver receives the data byte it must generate an acknowledge bit known as TXAK on the 9th clock The slave device which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte if not then it will release the SDA line and await the receipt o...

Page 150: ...low Chart I2 C Time out Control In order to reduce the problem of I2 C lockup due to reception of erroneous clock sources a time out function is provided If the clock source to the I2 C is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts counting on an I2 C bus START address match condition and is cleared by an...

Page 151: ...MD SIMA SIMC0 No change SIMC1 Reset to POR condition I2 C Registers after Time out The SIMTOF flag can be cleared by the application program There are 64 time out periods which can be selected using SIMTOS bit field in the SIMTOC register The time out time is given by the formula 1 64 32 fSUB This gives a time out period which ranges from about 1ms to 64ms SIMTOC Register Bit 7 6 5 4 3 2 1 0 Name ...

Page 152: ...e integrated UART function contains the following features Full duplex asynchronous communication 8 or 9 bits character length Even odd or no parity options One or two stop bits Baud rate generator with 8 bit prescaler Parity framing noise and overrun error detection Support for interrupt on address detect last character bit 1 Separately enabled transmitter and receiver 2 byte Deep FIFO Receive Da...

Page 153: ...ter is mapped onto the MCU Data Memory the Transmit Shift Register is not mapped and is therefore inaccessible to the application program Data to be received by the UART is accepted on the external RX pin from where it is shifted in LSB first to the Receiver Shift Register at a rate controlled by the Baud Rate Generator When the shift register is full the data will then be transferred from the shi...

Page 154: ... 6 NF Noise flag 0 No noise is detected 1 Noise is detected The NF flag is the noise flag When this read only flag is 0 it indicates no noise condition When the flag is 1 it indicates that the UART has detected noise on the receiver input The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun The NF flag can be cleared by a software sequence which w...

Page 155: ... set followed by a read from the TXR_RXR register and if the TXR_RXR register has no more new data available Bit 1 TIDLE Transmission idle 0 Data transmission is in progress Data being transmitted 1 No data transmission is in progress Transmitter is idle The TIDLE flag is known as the transmission complete flag When this read only flag is 0 it indicates that a transmission is in progress This flag...

Page 156: ...remain unaffected If the UART is active and the UARTEN bit is cleared all pending transmissions and receptions will be terminated and the module will be reset as defined above When the UART is re enabled it will restart in the same configuration Bit 6 BNO Number of data transfer bits selection 0 8 bit data transfer 1 9 bit data transfer This bit is used to select the data length format which can h...

Page 157: ...r also serves to control the baud rate speed receiver wake up enable and the address detect enable Further explanation on each of the bits is given below Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN UART Transmitter enabled control 0 UART transmitter is disabled 1 UART transmitter is enabled The bit named TXEN i...

Page 158: ... the WAKE bit is set to 1 as the UART clock fH is switched off a UART wake up request will be initiated when a falling edge on the RX pin occurs When this request happens and the corresponding interrupt is enabled an RX pin wake up UART interrupt will be generated to inform the MCU to wake up the UART function by switching on the UART clock fH via the application program Otherwise the UART functio...

Page 159: ...e value N in the BRG register which is used in the following baud rate calculation formula determines the division factor Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255 UCR2 BRGH Bit 0 1 Baud Rate BR fH 64 N 1 fH 16 N 1 By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register t...

Page 160: ...is disabled the buffer will be reset to an empty condition at the same time discarding any remaining residual data Disabling the UART will also reset the error and status flags with bits TXEN RXEN TXBRK RXIF OERR FERR PERR and NF being cleared while bits TIDLE TXIF and RIDLE will be set The remaining control bits in the UCR1 UCR2 and BRG registers will remain unaffected If the UARTEN bit in the UC...

Page 161: ...baud rate generator has defined a shift clock source However the transmission can also be initiated by first loading data into the TXR_RXR register after which the TXEN bit can be set When a transmission of data begins the TSR is normally empty in which case a transfer to the TXR_RXR register will result in an immediate transfer to the TSR If during a transmission the TXEN bit is cleared the trans...

Page 162: ...XBRK bit the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits If the BNO bit is set the word length will be set to 9 bits with the...

Page 163: ...s are generated if appropriate and the RIDLE bit is set A break is regarded as a character that contains only zeros with the FERR flag set If a long break signal has been detected the receiver will regard it as a data frame including a start bit data bits and the invalid stop bit and the FERR flag will be set The receiver must wait for a valid stop bit before looking for the next start bit The rec...

Page 164: ...wing will occur The read only noise flag NF in the USR register will be set on the rising edge of the RXIF bit Data will be transferred from the Shift register to the TXR_RXR register No interrupt will be generated However this bit rises at the same time as the RXIF bit which itself generates an interrupt Note that the NF flag is reset by a USR register read operation followed by a TXR_RXR registe...

Page 165: ...ciated flag but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register An RX pin wake up which is also a UART interrupt source does not have an associated flag but will generate a UART interrupt if the UART clock fH source is switched off and the WAKE and RIE bits in the UCR2 register are set when a falling ed...

Page 166: ...nsmission is still in progress then the transmission will be paused until the UART clock source derived from the microcontroller is activated In a similar way if the MCU switches off the UART clock fH and enters the IDLE or SLEEP mode by executing the HALT instruction while receiving data then the reception of data will likewise be paused When the MCU enters the IDLE or SLEEP mode note that the US...

Page 167: ...is less than 0 1s Being compliant with the ISO IEC 14443A Reader Writer Passive communication mode the NFC module can be read written by other NFC devices within a communication distance of less than 10cm An NFC EEPROM and an NFC SRAM are provided for user defined data while a series of registers are available for the NFC function control and an NFC command set is also offered to implement differe...

Page 168: ...ID4 D7 D6 D5 D4 D3 D2 D1 D0 1 01H 06H UID5 D7 D6 D5 D4 D3 D2 D1 D0 1 01H 07H UID6 D7 D6 D5 D4 D3 D2 D1 D0 2 02H 08H BCC1 D7 D6 D5 D4 D3 D2 D1 D0 2 02H 09H Internal D7 D6 D5 D4 D3 D2 D1 D0 2 02H 0AH SLOCK0 L7 L6 L5 L4 LCC BL15 10 BL9 4 BLCC 2 02H 0BH SLOCK1 L15 L14 L13 L12 L11 L10 L9 L8 3 03H 0CH CC0 D7 D6 D5 D4 D3 D2 D1 D0 3 03H 0DH CC1 D7 D6 D5 D4 D3 D2 D1 D0 3 03H 0EH CC2 D7 D6 D5 D4 D3 D2 D1 D0...

Page 169: ...e corresponding page becomes read only memory Bit 3 LCC Capability Container static lock bit The Capability Container located in page 3 can be locked by setting the lock bit LCC to 1 to prevent further write access After being locked the page becomes read only memory Bit 2 BL15 10 Page 15 10 block lock bit If this bit is set to 1 the lock configuration for the corresponding memory area i e the con...

Page 170: ...it 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W Default 0 0 0 1 0 0 0 0 Bit 7 4 D7 D4 Major version number Bit 3 0 D3 D0 Minor version number CC2 Byte Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W Default 0 0 1 0 0 1 1 0 Bit 7 0 D7 D0 Define available memory size for NFC Data Exchange Format NDEF messages Data area size CC2...

Page 171: ...ity with different NFC devices it is not recommended to change the default capability container contents Page 3 default value initial state Bytes CC0 CC1 CC2 CC3 Default Value 11100001 00010000 00100110 00000000 Write command to page 3 CCn Byte Bytes CC0 CC1 CC2 CC3 Written Value 00000000 00000000 00000000 00001111 The written value will not be directly written into the corresponding CCn byte An O...

Page 172: ...sable 1 Enable To enable this interrupt function both of the MRDE bit and the NFC overall interrupt enable bit NFCE should be set high Bit 6 MWRE MCU writing NFC memory complete interrupt control 0 Disable 1 Enable To enable this interrupt function both the MWRE bit and the NFC overall interrupt enable bit NFCE should be set high Bit 5 NRDE RF reading NFC memory complete interrupt control 0 Disabl...

Page 173: ... 0 by the application program Bit 6 MWRF MCU writing to the NFC memory complete interrupt request flag 0 MCU writing to the NFC memory has not completed 1 MCU writing to the NFC memory has completed If the MCU has finished writing to the NFC memory this flag together with the NFC interrupt flag NFCF will both be set high by the hardware When this condition occurs the corresponding interrupt will o...

Page 174: ...cified field condition detected If a field condition defined by the FCONF1 FCONF0 bits occurs this flag together with the NFC interrupt flag NFCF will both be set high by the hardware When this condition occurs the corresponding interrupt will occur if the interrupt function is enabled Note that this bit can only be cleared to 0 by the application program Bit 0 ERF MCU or RF access NFC memory erro...

Page 175: ...it is high after the MCU accesses the NFC memory it means that the RF access collision has happened and the current access to the NFC memory by the MCU is not successful Bit 0 HFPON NFC field status flag 0 NFC field inactive 1 NFC field active This bit is used to indicate the NFC field activity status When there is no external RF device close to the MCU the HFPON bit will be low and the relevant N...

Page 176: ...se for MCU write operation control 0 Disable 1 Enable This is the NFC memory page address automatic increase control bit which must be set high before MCU write operations are carried out Clearing this bit to zero will inhibit the NFC memory page address automatic increase for MCU write operations If the NFC page address reaches 0x4Fh then the next page address will be 0x00h If the error interrupt...

Page 177: ... NFC page address register is set with a value from 0x50h to 0x7Fh this bit will be reset to zero by the hardware after the NFC page address has changed If the error interrupt request WIPF RIPF or ERF occurs this bit will also be automatically reset to zero by the hardware Bit 0 NFCRD MCU read NFC memory control 0 Read cycle has finished 1 Activate a read cycle This is the MCU reading NFC memory c...

Page 178: ...nded to set this bit high to enable the NFC function at the beginning of the application program The NFC function will be actually enabled when both the NFCEN and HFPON bits are set high NFCWRA Register Bit 7 6 5 4 3 2 1 0 Name WRA6 WRA5 WRA4 WRA3 WRA2 WRA1 WRA0 R W R R R R R R R POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 0 WRA6 WRA0 Last NFC memory page address written by RF Collisions...

Page 179: ... the appropriate response will be generated accordingly NFC Circuit Enabled NFC Field present NFCEN 1 HFPON 1 IDLE HALT READY 1 READY 2 ACTIVE Anticollision CL1 Anticollision CL2 REQA WUPA WUPA Select CL1 Select cascade level 1 Select CL2 Select cascade level 2 READ page 0x00h 0x0Fh HLTA READ FAST_READ WRITE COMPATIBILITY_WRITE GET_VERSION READY 1 READY 2 ACTIVE Anticollision CL1 Anticollision CL2...

Page 180: ...an one NFC tag device is in the NFC field the READ command accessed from page 0x00h 0x0Fh will cause a collision due to the different UID data bytes transmitted by these NFC tag devices READY2 State When a Select CL1 command is received by the NFC tag device in the READY1 state the NFC tag device will exit the READY1 state and then enter the READY2 state There are three methods to exit the READY2 ...

Page 181: ...l return to the IDLE or HALT state depending on its previous state HALT State When a halt command HLTA is successfully executed in the ACTIVE state the NFC tag will enter the HALT state The only way to exit the HALT state is with the execution of the WUPA command Any other command received in the HALT state will be interpreted as an error and the NFC tag device will stay in the HALT state An NFC t...

Page 182: ...cording to ISO IEC 14443 3 52 Command Tag Device Response CMD 7 bit 44 00 ATQA 90μs WUPA Execution Diagram Anticonllision CL1 Anticollision Command for Cascade Level 1 Select CL1 Select Command for Cascade Level 1 Command Code CMD Parameter PAR Data Integrity Mechanism Response Anticollision CL1 93h 20h Parity BCC0 3 bytes CL1 UID Anticollision CL1 93h 21h to 67h Part of CL1 UID Parity BCC0 Part o...

Page 183: ... Part of CL2 UID Parity BCC1 Part of CL2 UID Select CL2 95h 70h 4 bytes selected UID Parity BCC1 CRC SAK 00h The Anticollision and Select commands for Cascade Level 2 are based on the same command code The main difference between these two commands is the parameter byte The parameter byte is defined as 70h for the Select commands while this field is defined from 20h to 67h for the Anticollision co...

Page 184: ...will be internally incremented by one The valid page start address ranges from 00h to 4Fh For example if the page start address is set to 2Eh the data in page 2Eh 2Fh 30h and 31h will then be sent out sequentially Any invalid page address in the parameter field will result in an error resulting in a 4 bit NAK signal with a value of 0h being returned by the tag device A roll over mechanism is provi...

Page 185: ...ag device remains 50 Command Tag Device Response CMD NAK 90μs 00 CRC0 CRC1 PAR CRC error ACK 90μs HLTA Execution Diagram WRITE Write Command Code CMD Parameter PAR Data Integrity Mechanism Response A2h ADR 02h to 4Fh 4 Bytes Parity CRC ACK or NAK The WRITE command is used to program the NFC tag device memory by page with 4 data bytes The page address is specified in the parameter field The availab...

Page 186: ...C0 CRC1 D15 D3 D4 ADR CRC Parity error 90μs ACK NAK 90μs A0 Command Tag Device Response CMD ADR CRC0 CRC1 PAR D0 CRC0 CRC1 D15 CRC Parity error D3 D4 tCOL Collision time including tRCY or tWCY respectively tCOL exists if the collision of the NFC memory access by MCU occurs A0 Command Tag Device Response CMD ACK ADR CRC0 CRC1 D0 CRC0 CRC1 D15 NAK PAR 90μs D3 D4 Write error 2tWCY Response time tCOL ...

Page 187: ... bit is 0 the total memory size is exactly 2n bytes However the total memory size will be greater than 2n bytes but less than 2 n 1 bytes if the least significant bit is equal to 1 The memory size for this NFC tag device is 304 bytes which is greater than 256 bytes and less than 512 bytes Therefore the most significant 7 bits of Byte 6 is the value of 0001000b which is equal to 8 in decimal and th...

Page 188: ...ue i e invalid page address 1h NAK for parity or CRC error 5h NAK for EEPROM write error ATQA Response The NFC tag device will send 2 bytes of data known as ATQA as a response to a REQA or WUPA command The 2 byte ATQA value is first sent out with the least significant byte 44h Hex Value Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 44h 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Note bit8 and bit7 of the ATQA...

Page 189: ...MC register which in addition to controlling the overall on off function also controls the R type bias current on the SCOMn pins This enables the LCD COM driver to generate the necessary voltage levels VSS VDD 2 and VDD for LCD 1 2 bias operation The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver The SCOMn pin is selected to be used for LCD driving by the corresp...

Page 190: ...gister Bit 7 6 5 4 3 2 1 0 Name ISEL1 ISEL0 SCOMEN R W R W R W R W POR 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 5 ISEL1 ISEL0 SCOM typical bias current selection VDD 5V 00 25μA 01 50μA 10 100μA 11 200μA Bit 4 SCOMEN Software controlled LCD driver enable control 0 Disable 1 Enable The SCOMn lines can be enabled using the corresponding pin shared selection bits if the SCOMEN bit is set to 1 When th...

Page 191: ...lication program is controlled by a series of registers located in the Special Purpose Data Memory as shown in the accompanying table The first is the INTC0 INTC3 registers which setup the primary interrupts the second is the MFI0 MFI2 registers which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a nu...

Page 192: ...ad as 0 Bit 3 2 INT1S1 INT1S0 Interrupt edge control for INT1 pin 00 Disable 01 Rising edge 10 Falling edge 11 Both rising and falling edges Bit 1 0 INT0S1 INT0S0 Interrupt edge control for INT0 pin 00 Disable 01 Rising edge 10 Falling edge 11 Both rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Name MF0F CPF INT0F MF0E CPE INT0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bi...

Page 193: ...upt request Bit 5 MF2F Multi function 2 interrupt request flag 0 No request 1 Interrupt request Bit 4 MF1F Multi function 1 interrupt request flag 0 No request 1 Interrupt request Bit 3 TB0E Time Base 0 interrupt control 0 Disable 1 Enable Bit 2 ADE A D Converter interrupt control 0 Disable 1 Enable Bit 1 MF2E Multi function 2 interrupt control 0 Disable 1 Enable Bit 0 MF1E Multi function 1 interr...

Page 194: ... W R W R W POR 0 0 Bit 7 5 Unimplemented read as 0 Bit 4 NFCF NFC interrupt request flag 0 No request 1 Interrupt request Bit 3 1 Unimplemented read as 0 Bit 0 NFCE NFC interrupt control 0 Disable 1 Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name STMAF STMPF STMAE STMPE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 STMAF STM Comparator A match interrupt request flag 0 No requ...

Page 195: ...ag 0 No request 1 Interrupt request Bit 3 CTMAE CTM Comparator A match interrupt control 0 Disable 1 Enable Bit 2 CTMPE CTM Comparator P match interrupt control 0 Disable 1 Enable Bit 1 PTMAE PTM Comparator A match interrupt control 0 Disable 1 Enable Bit 0 PTMPE PTM Comparator P match interrupt control 0 Disable 1 Enable MFI2 Register Bit 7 6 5 4 3 2 1 0 Name DEF LVF DEE LVE R W R W R W R W R W P...

Page 196: ...ith a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable bits together with their associated request flags are shown in the Accompanying diagrams with their order of priority Some interrupt sources have their own individual vector while other...

Page 197: ...ternal interrupt enable bit INT0E INT1E must first be set Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type As the external interrupt pins are pin shared with I O pins they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding in...

Page 198: ... bit will be automatically cleared to disable other interrupts However it must be noted that although the Multi function Interrupt request flags will be automatically reset when the interrupt is serviced the request flags from the original source of the Multi function interrupts will not be automatically reset and must be manually reset by the application program A D Converter Interrupt The device...

Page 199: ... 4 fSYS fSUB Prescaler 0 CLKSEL0 1 0 fPSC0 fPSC0 28 fPSC0 215 M U X M U X TB0 2 0 TB1 2 0 Time Base 0 Interrupt Time Base 1 Interrupt TB0ON TB1ON M U X fSYS 4 fSYS fSUB Prescaler 1 CLKSEL1 1 0 fPSC1 fPSC1 28 fPSC1 215 Time Base Interrupts PSC0R Register Bit 7 6 5 4 3 2 1 0 Name CLKSEL01 CLKSEL00 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 CLKSEL01 CLKSEL00 Prescaler 0 clock source ...

Page 200: ...pt enable bit SIME must first be set When the interrupt is enabled the stack is not full and any of the above described situations occurs will take place When the Serial Interface Module Interrupt is serviced the interrupt request flag SIMF will be automatically reset and the EMI bit will be cleared to disable other interrupts UART Transfer Interrupt The UART Transfer Interrupt is controlled by se...

Page 201: ...nabled the stack is not full and an EEPROM Write cycle ends a subroutine call to the respective Multi function Interrupt vector will take place When the EEPROM Write Interrupt is serviced the EMI bit will be automatically cleared to disable other interrupts However only the Multi function interrupt request flag will be automatically cleared As the DEF flag will not be automatically cleared it has ...

Page 202: ...revented from being serviced however once an interrupt request flag is set it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request ﬂag is cleared by the application program Where a certain interrupt is contained within a Multi function interrupt then when the interrupt service routine is executed as only the Multi function inter...

Page 203: ...bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector circuits As the low voltage detector will consume a certain amount of ...

Page 204: ...Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions VDD LVDEN LVDO VLVD tLVDS LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi function interrupts providing an alternative means of low voltage detection in addition to polling the LVDO bit The interr...

Page 205: ...ed they cannot be changed later using the application program All options must be defined for proper system function the details of which are shown in the table No Options Oscillator Options 1 HIRC frequency selection for writer trim EV trim code use only 1 4MHz 2 8MHz 3 12MHz 2 HXT mode selection for Low Voltage mode 1 By S W 2 HXT 10MHz or HXT 8MHz 1 8V Note When the HIRC has been configured at ...

Page 206: ...reader can read the information stored in the tag The function of the NFC system coil circuit is divided into two parts one is to use radio frequency signals to generate power the other is to receive and transmit data by means of signal modulation Generally the reader will first emit a radio scan signal with a frequency of 13 56MHz If a passive NFC tag presents within the scan range it can receive...

Page 207: ... reader or NFC mobilephone to communicate with the HT45F4050 NFC module via the NFC interface the HT45F4050 NFC module uses the SPI interface to communicate with the Flash memory on board 3 Regarding the data storage stage the power of the data logger demo board is supplied by a button battery and the sensor data are stored into the Flash Memory at fixed intervals Data logging is implemented using...

Page 208: ...D HT45F4050 T R1 833ET 2 C1 0 1uF VDD R7 1K R8 1K R9 1K R17 1K R18 1K CE1 10uF R4 4 7K R5 4 7K C7 0 1uF C10 100nF CE3 10uF L1 C2 20pF R12 1K R13 1K SW1 STOP SW2 START VDD LA AVSS VDD LB PF5 XT1 PF4 XT2 PC5 AN5 PC4 AN4 PB3 CTP PA4 SDI SDA PA5 SCK SCL PB0 CX PD2 AN10 PB2 PTCK PTPB PE3 VDDIO CTP PE2 CTCK CTPB PE1 STPI STP PE0 STCK STPB PA7 INT1 TX PA6 INT0 RX PF2 SDI SDA SCOM2 PF3 SCK SCL SCOM3 PF0 S...

Page 209: ...to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one cycle ...

Page 210: ...ructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual Bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of certai...

Page 211: ...ry result in Data Memory 1Note Z C AC OV SC CZ DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1No...

Page 212: ...urn from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None ITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL m Increment table pointer TBLP first and Read table ...

Page 213: ...ust ACC for Addition with result in Data Memory 2Note C Logic Operation LAND A m Logical AND Data Memory to ACC 2 Z LOR A m Logical OR Data Memory to ACC 2 Z LXOR A m Logical XOR Data Memory to ACC 2 Z LANDM A m Logical AND ACC to Data Memory 2Note Z LORM A m Logical OR ACC to Data Memory 2Note Z LXORM A m Logical XOR ACC to Data Memory 2Note Z LCPL m Complement Data Memory 2Note Z LCPLA m Complem...

Page 214: ... in ACC 2Note None Table Read LTABRD m Read table to TBLH and Data Memory 3Note None LTABRDL m Read table last page to TBLH and Data Memory 3Note None LITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL m Increment table pointer TBLP first and Read table last page to TBLH and Data Memory 3Note None Miscellaneous LCLR m Clear Data Memory 2Note Non...

Page 215: ...and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C SC ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC AND A m Logical AND Data Memory to ACC Description Data...

Page 216: ...usly contained a 1 are changed to 0 and vice versa Operation m m Affected flag s Z CPLA m Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented 1 s complement Bits which previously contained a 1 are changed to 0 and vice versa The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged Ope...

Page 217: ... m m 1 Affected flag s Z INCA m Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1 The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC m 1 Affected flag s Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address Program execution ...

Page 218: ...Z RET Return from subroutine Description The Program Counter is restored from the stack Program execution continues at the restored address Operation Program Counter Stack Affected flag s None RET A x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data Program execution continu...

Page 219: ...laces the Carry bit and the original carry flag is rotated into the bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 C C m 7 Affected flag s C RR m Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7 Operation m i m i 1 i 0 ...

Page 220: ...C Affected flag s OV Z AC C SC CZ SBCM A m Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Data Memory Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or z...

Page 221: ...le the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m 1 Skip if ACC 0 Affected flag s None SNZ m i Skip if Data Memory is not 0 Description If the specified Data Memory is not 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is...

Page 222: ...re interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it ...

Page 223: ...peration m program code low byte TBLH program code high byte Affected flag s None ITABRDL m Increment table pointer low byte first and read table last page to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operat...

Page 224: ... the Accumulator Operation ACC ACC m Affected flag s OV Z AC C SC LADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC LAND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitw...

Page 225: ...igh nibble is greater than 9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operati...

Page 226: ...otated left by 1 bit with bit 7 rotated into bit 0 Operation m i 1 m i i 0 6 m 0 m 7 Affected flag s None LRLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0...

Page 227: ... and the carry flag are rotated right by 1 bit Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 C C m 0 Affected flag s C LSBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the c...

Page 228: ...he specified Data Memory is set to 1 Operation m i 1 Affected flag s None LSIZ m Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is not 0 th...

Page 229: ... 1 Operation m ACC m Affected flag s OV Z AC C SC CZ LSWAP m Swap nibbles of Data Memory Description The low order and high order nibbles of the specified Data Memory are interchanged Operation m 3 m 0 m 7 m 4 Affected flag s None LSWAPA m Swap nibbles of Data Memory with result in ACC Description The low order and high order nibbles of the specified Data Memory are interchanged The result is stor...

Page 230: ...lag s None LITABRD m Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the program code addressed by the table pointer TBHP and TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None LITABRDL m Increment ...

Page 231: ...ntervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Meterials Information Carton i...

Page 232: ... B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 020 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 000 BSC B 7 000 BSC C 9 000 BSC D 7 000 BSC E 0 500 BSC F 0 170 0 220 0 270 G 1 350 1 400 1 450 H 1 600 I 0 050 0 150 J 0 450 0 600 0 750 K 0 090 0 200 α 0 7 ...

Page 233: ...ely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserves the ...

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