Hitachi L32VK06U, Service Manual

Page: 56 / 113

15.1.5 Pinning
15.2 74HCT4053
15.2.1 General Description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The
74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select inputs
(Sn). With E LOW, one of the two switches is selected (low-impedance ON-state) by S1 to
S3. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 to
S3. VCC and GND are the supply voltage pins for the digital control inputs (S1 to S3 and
E). The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 and nY1, and nZ) can swing between VCC
as a positive limit and VEE as a negative limit. VCC - VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
15.2.2 Features
x
Low ON resistance:
x
80 W (typical) at VCC - VEE = 4.5 V
x
70 W (typical) at VCC - VEE = 6.0 V
x
60 W (typical) at VCC - VEE = 9.0 V
x
Logic level translation:
x
To enable 5 V logic to communicate with ±5 V analog signals
x
Typical ‘break before make’ built in
x
Complies with JEDEC standard no. 7A
x
ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V, MM EIA/JESD22-
A115-A exceeds 200 V
x
Multiple package options
x
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
15.2.3 Applications
x
Analog multiplexing and demultiplexing
x
Digital multiplexing and demultiplexing
x
Signal gating