3V3IO
R66
10k
3V3IO
3V3IO
10k
R36
TP1
S2
C252
100n
16V
3V3IO
10k
R14
R6
10k
10k
R7
R10
10k
10k
R11
R1
10k
10k
R2
10k
R12
R13
10k
R3
10k
R39
10k
10k
R48
10k
R37
R38
10k
R45
10k
3V3IO
10k
R47
10k
R46
R8
10k
10k
R9
R4
10k
10k
R5
R21
10k
R22
10k
10k
R25
R26
10k
10k
R17
R18
10k
R15
10k
R16
10k
10k
R19
R20
10k
10k
R23
R24
10k
3V3IO
R27
10k
74V1G08
U21
5
4
3
2
1
A
B
GND
Y
VCC
10k
R28
10k
R49
16V
100n
C254
C247
100n
16V
C248
16V
100n
3V3IO
3V3IO
10k
R44
S29GL064NFFI
U2
E2
D2
C2
A2
B2
D3
C3
A3
B6
A6
C6
D6
B7
A7
C7
D7
E7
B3
C4
D5
D4
C5
B8
C8
F8
F2
G2
B5
A5
D8
F1
E3
H3
E4
H4
H5
E5
H6
E6
F3
G3
F4
G4
F5
G6
F6
G7
A1
A8
B1
C1
D1
E1
G1
G8
H1
H8
A4
F7
B4
G5
E8
H2
H7
VSS3
VSS2
VSS1
VCC
WP#/ACC
BYTE#
RY/BY#
NC_10
NC_9
NC_8
NC_7
NC_6
NC_5
NC_4
NC_3
NC_2
NC_1
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VIO2
VIO1
WE#
RESET#
OE#
CE#
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
uPD61305F1
U1
AA16
AC15
AB16
V21
AC16
V23
U21
AD26
W23
AB20
AA20
AA19
V22
Y22
AC25
W22
Y23
AF26
AC26
Y21
W21
AB24
AD25
AB13
AA13
W24
AE26
AF17
AE17
AD17
AC17
AB17
AA17
AF18
AE18
AD18
AB18
AA18
AE19
AD19
AC19
AB19
AD20
AF20
AE20
AF21
AE21
AD21
AC21
AB21
AA21
AF22
AE22
AD22
AC22
AB22
AA22
AF23
AE23
AD23
AC23
AB23
AA23
AF24
AE24
AD24
AC24
AF25
AE25
RADD0
RADD1
RADD2
RADD3
RADD4
RADD5
RADD6
RADD7
RADD8
RADD9
RADD10
RADD11
RADD12
RADD13
RADD14
RADD15
RADD16
RADD17
RADD18
RADD19
RADD20
RADD21
RADD22
RADD23
RADD24
RADD25
RDATA0
RDATA1
RDATA2
RDATA3
RDATA4
RDATA5
RDATA6
RDATA7
RDATA8
RDATA9
RDATA10
RDATA11
RDATA12
RDATA13
RDATA14
RDATA15
FCSB0
FCSB1
FCSB2
FCSB3
FOEB
FWEB
GCSB0
GCSB1
GPIO_CD1B
GPIO_CD2B
GPIO_IREQB
GPIO_RESET
GPIO_VS1B
GRDYB
IOIS16
IORDB
IOWRB
NALE
NCLE
NR/BB
PCE0B
PCE1B
REGB
SMVCC1
STP0CLK
STP0EN
STP0STRT
4
3V3IO
NEC FLASH
MB38-1
19
14
A
B
C
D
E
F
1
2
3
4
5
6
7
8
OF:
A3
PROJECT NAME :
SCH NAME :
DRAWN BY :
SHEET:
04-12-2009_16:33
nCI_IRQ
FWEB_FLASH
FWEB_FLASH
nRESET
RADD19
RADD19
RADD19
RADD18
RADD18
RADD18
RADD17
RADD17
RADD17
RADD16
RADD16
RADD16
RADD15
RADD15
RADD15
RADD14
RADD14
RADD14
RADD13
RADD13
RADD13
RADD12
RADD12
RADD12
RADD11
RADD11
RADD11
RADD10
RADD10
RADD10
RADD9
RADD9
RADD9
RDATA15
RDATA15
RDATA14
RDATA14
RDATA13
RDATA13
RDATA12
RDATA12
RDATA11
RDATA11
RDATA10
RDATA10
RDATA9
RDATA9
RADD7
RADD7
RADD7
RADD8
RADD8
RADD8
RADD6
RADD6
RADD6
RADD5
RADD5
RADD5
RADD4
RADD4
RADD4
RADD3
RADD3
RADD3
RADD2
RADD2
RADD2
RADD1
RADD1
RADD1
RADD0
RADD0
FCSB0
FCSB0
FWEB
FWEB
FOEB
FOEB
RDATA8
RDATA8
RDATA7
RDATA7
RDATA6
RDATA6
RDATA5
RDATA5
RDATA4
RDATA4
RDATA3
RDATA3
RDATA2
RDATA2
RDATA1
RDATA1
RDATA0
RDATA0
RADD25
RADD25
RADD24
RADD24
RADD23
RADD23
RADD22
RADD22
RADD21
RADD21
RADD20
RADD20
nCI_PWR
nCI_REG
nCS2
nCI_IOWR
nCI_VS
nCI_CD1
nCI_CD2
nCI_RESET
nRDY
nCI_IORD
NC
NC
FAST FLASH PROGRAMMING OPTION
RADD19 EJTAG Daisy Chain Setting 0=Reserved 1=Only Main CPU
RADD18 EJTAG DINT Enable Setting 0=Disable 1=Enable
RADD17 EJTAG or JTAG Setting 0=JTAG 1=EJTAG
RADD16 Test Please set 0.
RADD15 Test Please set 0.
RADD14 Test Please set 0.
RADD13 NAND Flash ROM CS pin selection 0=CS0 1=CS1
other: Prohibit
(if normal NAND Flash ROM is 512 Mb or less)
01: Address latch cycle: 4 times, command latch cycle: once
(if normal NAND Flash ROM is 256 Mb or less)
00: Address latch cycle: 3 times, command latch cycle: once
program is stored in the NAND boot mode (BOOT_MODE = 001 or 011)
Specifies the access method of NAND Flash ROM where the boot
Boot NAND ROM selection
RADD12 BOOT_NAND_SEL[1]
RADD11 BOOT_NAND_SEL[0]
other: Prohibit
011: Boot from the NAND Flash ROM or Memory Stick
001: Boot from the NAND Flash ROM
000: Normal (Not Mini Boot)
Boot mode setting: BOOT_MODE[2:0] =
RADD10 BOOT_MODE[2]
RADD9 BOOT_MODE[1]
RADD8 BOOT_MODE[0]
RADD7 ROM bus width setting 0=16-bit 1=8-bit
RADD6 ROM endian Setting 0=Little 1=Big
1:262.144 MHz
0: 327.680 MHz
MCLK_SEL=
RADD5 MCLK_SEL Unified memory clock frequency selection
11: Reserved (setting prohibited)
10: 218.450 MHz
01: 262.144 MHz
00: 327.680 MHz
CPUCLK_SEL[1:0]=
Main CPU clock frequency selection
RADD4 CPUCLK_SEL[1]
RADD3 CPUCLK_SEL[0]
RADD2 Test Please set 0.
RADD1 Test Please set 0.
RADD0 CPU endian Setting 0=Little 1=Big
Signal Description
STRAP OPTIONS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Summary of Contents for L32VK06U
Page 19: ...3 6 Absolute Ratings 3 6 1 Electrical Characteristics 3 6 2 Operating Specifications ...
Page 27: ...6 3 Absolute Maximum Ratings ...
Page 29: ...7 3 Absolute Maximum Ratings 7 4 Pinning ...
Page 30: ......
Page 33: ...8 3 Absolute Maximum Rating ...
Page 34: ...8 4 Pinning ...
Page 35: ......
Page 36: ......
Page 38: ...9 3 Absolute Maximum Ratings 9 4 Pinning ...
Page 39: ......
Page 41: ...11 4 Pinning ...
Page 44: ...11 4 Pinning ...
Page 45: ......
Page 47: ......
Page 51: ...11 4 Pinning ...
Page 54: ......
Page 57: ...15 2 4 Absolute Maximum Ratings 15 2 5 Pinning ...
Page 66: ...15 9 3 Absolute Maximum Ratings 15 9 4 Pinning ...
Page 68: ...15 10 3 Absolute Maximum Ratings 15 10 4 Pinning ...
Page 71: ...15 12 3 Absolute Maximum Ratings 15 12 4 Pinning ...
Page 74: ...15 14 3 Absolute Maximum Ratings 15 14 4 Pinning ...
Page 76: ...15 15 4 Pinning ...
Page 79: ...15 17 3 Absolute Maximum Ratings 15 17 4 Pinning ...
Page 81: ...15 18 3 Absolute Maximum Ratings 15 18 4 Pinning ...
Page 90: ...17 BLOCK DIAGRAM ...
Page 91: ...EXPLODED VIEW L32VK06U ...
Page 92: ...EXPLODED VIEW L42VK06U ...
Page 93: ...FOR ALL PARTS PLEASE MAKE CONTACT WITH ASWO FOR YOUR LOCAL OUTLET GO TO www aswo com ...