Hitachi L32VK06U, Service Manual

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10 ELPIDA EDE5116AJBG DDR SDRAM
10.1 General Description
There are 2 Elpida EDE5116AJBG (32M x 16 bits) DDR2 SDRAM used for NEC
EMMA3SL microcontroller functions and MPEG2/MPEG4 decoding functions. Data pins
are connected parallel and the address selection is varied for different memory access
locations.
10.2 Features
• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data
for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both
edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus
efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4
organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation
11.3 Absolute Maximum Ratings