Descriptions and drawings
25/82
Pin
Signal options: Communication interfaces and digital I/O
X600 netX
90
UART
XC
GPIO
IO Link
Ethernet
PIO
(APP CPU)
XM
CAN
MLED
35
D3
–
–
–
–
–
–
–
–
–
36
D2
–
–
–
–
ETH_TXCLK
–
–
–
–
37
D1
–
–
–
–
ETH_TXEN
–
–
–
–
38
C1
–
–
–
–
ETH_TXD3
–
–
–
–
39
B2
–
–
GPIO7
–
ETH_TXD2
–
–
–
–
40
C2
–
–
GPIO6
–
ETH_TXD1
–
–
–
–
41
A3
–
–
GPIO5
–
ETH_TXD0
–
–
–
–
42
B3
–
–
GPIO4 IO_LINK1B
_WAKEUP
ETH_RXDV
–
–
–
–
43
C3
–
–
GPIO3 IO_LINK1B
_OE
ETH_RXD3
–
–
–
–
44
A4
–
–
GPIO2 IO_LINK1B
_OUT
ETH_RXD2
–
–
–
–
45
B4
–
–
GPIO1 IO_LINK1B
_IN
ETH_RXD1
–
–
–
–
46
C4
–
–
GPIO0 IO_LINK0B
_WAKEUP
ETH_RXD0
–
–
–
–
47
A5
–
–
–
IO_LINK0B
_OE
ETH_CRS
–
–
CAN0_AP
P_TX
–
48
B5
–
–
–
IO_LINK0B
_OUT
ETH_COL
–
–
CAN0_AP
P_RX
–
49
C5
UART_XPIC
_APP_TXD
–
–
IO_LINK0B
_IN
ETH_TXER
–
–
–
–
50
–
–
–
–
–
–
–
–
–
–
51
A6
–
–
–
IO_LINK7_
WAKEUP
–
–
–
–
MLED1
1
52
B6
–
–
–
IO_LINK6_
WAKEUP
–
–
–
–
MLED1
0
53
C6
–
–
–
IO_LINK5_
WAKEUP
–
–
–
–
MLED9
54
A7
–
–
–
IO_LINK4_
WAKEUP
–
–
–
–
MLED8
55
B7
–
–
–
IO_LINK3_
WAKEUP
–
–
–
–
MLED7
56
C7
–
–
–
IO_LINK2_
WAKEUP
–
–
–
–
MLED6
57
A8
–
–
–
–
–
–
–
–
MLED5
58
B8
–
–
–
–
–
–
–
–
MLED4
59
C8
–
–
–
–
–
PIO_APP7
–
CAN1_AP
P_TX
–
60
A9
–
–
–
–
–
PIO_APP6
–
CAN1_AP
P_RX
–
Table 16: Signal options of X600 pins – communication interfaces and digital I/O (2)
NXHX 90-JTAG | Device description
DOC170202HW03EN | Revision 3 | English | 2019-01 | Released | Public
© Hilscher 2019