Accessories
44/72
Pinning of X1 host interface of NXHXSDRSPI device
See position
(2)
in figure above.
Pin
Signal
Pin
Signal
1
+3.3 V
35
SD_BA0
2
GND
36
SD_DQM0#
3
SD_CAS#
37
SD_A12
4
SD_CLK
38
SD_A11
5
GND
39
SD_A10
6
40
SD_A9
7
SD_RAS#
41
SD_A8
8
SD_D15
42
SD_A7
9
SD_D10
43
SD_A6
10
SD_D8
44
SD_A5
11
45
SD_A4
12
SD_CKE
46
SD_A3
13
GND
47
SD_A2
14
48
SD_A1
15
49
SD_A0
16
SD_WE#
50
GND
17
SD_D11
51
18
SD_D9
52
19
SD_DQM1#
53
SPM_SIRQ#
20
GND
54
SPM_DIRQ#
21
SD_D14
55
SPM_CLK
22
56
SPM_CS#
23
57
SPM_MOSI
24
SD_CS#
58
SPM_MISO
25
GND
59
SD_D7
26
SD_D13
60
SD_D6
27
SD_D12
61
SD_D5
28
62
SD_D4
29
63
SD_D3
30
64
SD_D2
31
65
SD_D1
32
66
SD_D0
33
GND
67
+3.3 V
34
SD_BA1
68
Table 49: Pinning host interface X1 of NXHXSDRSPI device
Pinning SPI interface X2 of NXHXSDRSPI device
See position
(3)
in figure above.
Pin
Signal
Pin
Signal
1
SPM_SIRQ#
7
SPM_CS#
2
+3.3 V
8
GND
3
SPM_DIRQ#
9
SPM_MOSI
4
GND
10
GND
5
SPM_CLK
11
SPM_MISO
6
GND
12
GND
Table 50: Pinning SPI interface X2 of NXHXSDRSPI device
NXHX 51ETM | Development Board
DOC120606HW06EN | Revision 6 | English | 201501 | Released | Public
© Hilscher 2012 – 2015