Harman Kardon AVR 171/230, Service Manual

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Data Sheet: DM Series
DM860A Networked Media Processor
dat_DM860A_1_1_datasheet.doc CONFIDENTIAL Version 1.1 – July 11
th
2011 - Page 19 of 70
2.11 NAND-Flash Interface
Name Pin(s) Type Description
FD[7:0] T17, T16, T15,
R17, R16, R15,
P16, P15 I/O Bi-directional data bus
FALE V18 O Address latch enable; pull-up/down defines boot mode
FCLE U16 O Command latch enable; pull-up/down defines boot mode
NFCE0 U15 O Chip-enable, low-active
NFRB U18 I Ready/busy. NAND flash is busy when NFRB is low.
NFRE V17 O Read enable, low-active
NFWE U17 O Write enable, low-active
NFWP V16 O Write protect, low-active
2.12 Ethernet MAC-Phy Interface (MII)
Name Pin Type MII RMII SMII
MIIDIO U14 I/O management data management data
MIIMDC V14 O management clock management clock
MIIRXD[3] V13 I RxD 3 RxD 1
MIIRXD[2] U13 I RxD 2 RxD 0
MIIRXD[1] V12 I RxD 1 Rx-Sync
MIIRXD[0] U12 I RxD 0 RxD
MIIRXCLK T12 I receive clock receive clock
MIIRXER R13 I receive error receive error
MIIRXDV T14 I receive data valid carrier sense/data valid
MIITXD[3] V11 O TxD 3 TxD 1
MIITXD[2] U11 O TxD 2 TxD 0
MIITXD[1] V10 O TxD 1 Tx-Sync
MIITXD[0] U10 O TxD 0 TxD
MIITXCLK R12 I transmit clock transmit clock
MIITXER T11 O transmit error
MIITXEN R11 O transmit data enable transmit data enable
MIICOL T13 I MII ethernet collision
MIICRS R14 I MII carrier sense
MIIPHYCLK V15 O 25.000 MHz clock 50.000 MHz clock 125.000 MHz clock
Harman Kardon AVR 171 Service Manual
Page 91 of 174