Data Sheet: DM Series
DM860A Networked Media Processor
dat_DM860A_1_1_datasheet.doc
CONFIDENTIAL
Version 1.1 – July 11
th
2011 - Page 15 of 70
2.2 Functional
Diagram
Please see Figure 2 for block diagram.
2.3 AV-Port
0
Name
Pin
Type Description
AV0DATA[3:0]
M4, N1, N2,
N3
I/O
Audio/video data. Several formats are supported, as described
in chapter 11
AV1DATA[3:0]
N4, P1, P2,
P3
I/O
Video data, together with AV0DATA[3:0]:
AV0DATA[3:0] =
video[3:0]
AV1DATA[3:0] = video[7:4]
AV0CLK L1
I/O
Data clock. Depending on the AV-Port 0 configuration, this
clock is a bit- or byte-clock which is used to transmit or receive
the AV0DATA[*] synchronously
AV0CTRL0
M1
I/O
Configurable sync signal:
serial audio formats: LRCK input or output
video formats:
PSYNC input or output
AV0CTRL1
M2
I/O
Configurable sync signal:
serial audio formats: master clock output
video formats:
DVALID input or output
AV0CTRL2
M3
I/O
Configurable sync signal:
video formats:
FSYNC input or output
2.4 AV-Port
2
Name
Pin
Type Description
AV2DATA[3:0]
P4, R3, T2,
U1
I/O
Audio data. Several formats are supported, as described in
chapter 11
AV2CLK R1
I/O
Data clock. Depending on the AV-Port 2 configuration this clock
is a bit-clock which is used to transmit or receive the
AV2DATA[*] synchronously
AV2CTRL0
T1
I/O
Configurable sync signal:
serial audio formats: LRCK input or output
AV2CTRL1
R2
I/O
Configurable sync signal:
serial audio formats: master clock output
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AVR 171 Service Manual
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