Grundig DVD-Kit1, Service Manual

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Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams DVD-Kit1
3 - 6 GRUNDIG Service
DVD
DVD
Front
End
Data
in
sync
detect
EDC
sync
CD-ROM
descramble
header
CSS
control
status
control
ints
I$
1024x32
D$
256x32
CPU
D$ Tag
256x20 I$ Tag
256x18
system
Timer Reset Watchdog
I$ control D$ control
I$ adr decode I$ rd mux D$ adr decodeD$ rd mux
Xbus interface
Interrupt
Routing
registers
Host MMU
BIU
32
AD
22
SPDIF
format
MMU HOST
ADC
input SPDIF
mod
PCM
out
AOP
primary
freq synth
audio
freq synth
oscillator
Event
Tagger
Video
Start
Code
Detector
Stream
Buffer
Write
Controller
PES/SI
Depacketizer
Program
Stream
Demux
Packet
Framer
HOST MMU
HOST
8
decrypt
UART0
UART1
SSP0
SSP1
Y line buffer
Cr line buffer
Cb line buffer
MMU
OSD
SPU
Scaler Merge
NTSC/PAL
& SCART
Encoder
HOST
Macrovision
CGMS
WSS
Cr/R
Y/G
C/Cb/B
VOP
VSD
MMU HOST
VIQ VRP
MMU HOST HOST
VIDEC
MMU HOST
DSP
I-ROM D-ROM
D-RAM
ASP
Arbiter
Module
Interfaces
HOST
regs
SDRAM
controller
address
generator
circular
buffer
Datapath
32
MD
MA
12
FIFO
128x8
DEMUX
HOST
Serial
Ports
10
ctrl
ctrl
MMU
7
11
DAC SPDIF MIC
sync serial
peripheral
sync serial
peripheral
async serial
peripheral
async serial
peripheral
HOST
PWM0 PWM1 PWM2
6
CVBS/C
Video Port
CCIR656 Port
video
freq synth
NAME TYPE PIN DESCRIPTION
Front End
DSYNC I 213 DVD parallel mode Sector Sync
DREQ O 214 DVD parallel mode Data Request
DCLK I 215 Data sampling clock
DSTB I 216 Parallel mode Data Valid, serial mode Left/Right Clock
DVD[7:0] I * DVD drive parallel data port, pins: 217, 219-223, 225, 226
External I/O
PCS0 O 193 Peripheral chip select 0, generally used for enabling the program store ROM/FLASH
XIO[14:1] B * Programmable general purpose I/O also used as peripheral chip select, interrupt, PWM output and other
system signals, pins: 195, 197-200, 202-203, 205-209, 211
SDRAM
MD[31:0] B * SDRAM data bus, pins: 227, 229, 231, 232, 234, 235, 236, 238, 239, 240, 2, 3, 5, 7, 8, 9, 43, 45, 46, 48, 50,
51, 52, 54, 55, 56, 58, 59, 60, 61, 63, 64
MA[11:0] O * SDRAM address bus, pins: 12, 13, 15, 16, 18, 20, 21, 25, 26, 28, 29, 30
MA[13:12] O 32-33 SDRAM address bus, reserved for pin compatibility with 64Mbit SDRAM
MCLK O 22 SDRAM clock
CKE O 24 SDRAM Clock Enable
CS0- O 35 SDRAM primary bank chip select
CS1- O 66 SDRAM extension bank chip select
RAS- O 37 SDRAM command bit
CAS- O 38 SDRAM command bit
WE- O 39 SDRAM command bit
DQM[3:0]- O 11, 41, 42, 65 SDRAM data byte enables
Host Interface
AD[31:0] B * mP multiplexed address/data bus
LA[3:0] B 184-187 Latched Address [3:0]
ALE B 183 Address Latch Enable
RD- B 189 Read
ACK- B 161 Programmable WAIT-/ACK-/RDY- control
SCLK O 160 External bus clock used for programmable host bus peripherals
PWE[3:0]- B * Byte write enable for FLASH, EEPROM, SRAM or peripherals, pins: 145, 156, 170, 182
Slave Mode
LHLD I 191 Bus Hold Request from external master in slave mode
LHLDA O 190 Bus Hold Acknowledge in slave mode
Comm Ports
UART1
RXD1 I 83 UART1 serial data input from external serial device, used for IR receive
SSP1
SSPCLK1/CTS1- B 87 SSP1 clock or UART1 Clear to Send signal
SSPOUT1/DTR1- B 86 SSP1 data out or UART1 Data Terminal Ready signal
SSPIN1/BAUD1 B 84 SSP1 data in or 16X clock for USART function in UART1