GOWIN GW1N-LV9LQ144C6I5 V1.1 User Manual Download Page 27

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3 FPGA Circuits

3.9 LVDS

DBUG398-1.1E

20(25)

Signal Name

Pin No.

40P Socket Pin No.

BANK Description

I/O

H_B_IO33

General I/O

VCCO1

H_B_IO34

General I/O

VCCO1

H_B_IO35

General I/O

VCCO1

H_B_IO36

General I/O

VCCO1

VCC5

GND

Note!

The VCCO1 of GW1N-9 can only be supplied with 3.3V.

3.9

LVDS

3.9.1

Overview

Two 2 mm DC3-20P sockets are reserved on the development board

for LVDS testing and data communication.

3.9.2

LVDS Circuit

Figure 3-8 LVDS Circuit

F_LVDS_A1_P

F_LVDS_A2_P

F_LVDS_A3_P

F_LVDS_A4_P

F_LVDS_A5_P

F_LVDS_A1_N

F_LVDS_A2_N

F_LVDS_A3_N

F_LVDS_A4_N

F_LVDS_A5_N

J10

F_LVDS_B1_P

F_LVDS_B2_P

F_LVDS_B3_P

F_LVDS_B4_P

F_LVDS_B5_P

F_LVDS_B1_N

F_LVDS_B2_N

F_LVDS_B3_N

F_LVDS_B4_N

F_LVDS_B5_N

J11

Summary of Contents for GW1N-LV9LQ144C6I5 V1.1

Page 1: ...DK_START_GW1N LV9LQ144C6I5_V1 1 User Guide DBUG398 1 1E 08 13 2021 ...

Page 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Page 3: ...Revision History Date Version Description 08 13 2021 1 0E Initial version published ...

Page 4: ...velopment Board Description 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Architecture 5 2 5 Features 6 2 6 Development Board Specification 7 3 FPGA Circuits 9 3 1 FPGA Module 9 3 2 Download Interface 9 3 2 1 Overview 9 3 2 2 USB Download Circuit 10 3 2 3 Downloading the Data Stream 10 3 2 4 Pinout 11 3 3 Power Supply 11 3 3 1 Overview 11 3 3 2 Power System Distr...

Page 5: ...5 2 LED Circuit 14 3 5 3 Pinout 14 3 6 Switches 14 3 6 1 Overview 14 3 6 2 Key Switch Circuit 15 3 6 3 Pinout 15 3 7 Key 15 3 7 1 Overview 15 3 7 2 Key Circuit 16 3 7 3 Pinout 16 3 8 GPIO 16 3 8 1 Overview 16 3 8 2 GPIO Circuit 17 3 8 3 Pinout 17 3 9 LVDS 20 3 9 1 Overview 20 3 9 2 LVDS Circuit 20 3 9 3 Pinout 21 4 Considerations 23 5 Gowin Software 25 ...

Page 6: ...B Components 5 Figure 2 4 System Architecture 5 Figure 3 1 Connection Diagram of FPGA USB Downloading and Configuration 10 Figure 3 2 Power System Distribution 12 Figure 3 3 Clock Reset 13 Figure 3 4 LED Circuit 14 Figure 3 5 Key Switch Circuit 15 Figure 3 6 Key Circuit Diagram 16 Figure 3 7 GPIO Circuit 17 Figure 3 8 LVDS Circuit 20 Figure 4 1 Download Speed 23 ...

Page 7: ...fication 7 Table 3 1 FPGA Download and Pinout 11 Table 3 2 GW1N 9 FPGA Power Pinout 12 Table 3 3 FPGA Clock and Reset Pinout 13 Table 3 4 LED Pinout 14 Table 3 5 Clock Circuit Pinout 15 Table 3 6 Key Pinout 16 Table 3 7 J8 FPGA Pinout 17 Table 3 8 J9 FPGA Pinout 19 Table 3 9 J10 FPGA Pinout 21 Table 3 10 J10 FPGA Pinout 21 ...

Page 8: ...evelopment board 4 Introduction to the use of the FPGA development software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com DS100 GW1N series of FPGA Products Data Sheet UG103 GW1N series of FPGA Products Package and Pinout UG114 GW1N 9 Pinout UG290 Gowin FPGA Products Programming and Configuration User Gui...

Page 9: ...nput Look up Tables SSRAM Shadow Static Random Access Memory BSRAM Block Static Random Access Memory PLL Phase locked Loop DLL Delay locked Loop DSP Digital Signal Processing LQ144 LQFP144 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly using the informatio...

Page 10: ...tures including low power consumption instant start up high security low cost and flexible extensions all of which can effectively reduce the learning cost and help users quickly design and develop programmable logic devices The development board includes two GPIO ports and two LVDS ports These provide users with a hardware evaluation and testing platform that offers a high integration level and s...

Page 11: ...daughter boards Motion control systems can also be designed by combining the development board with AD DA industrial daughter boards while human computer interface and image processing can be realized by combining the development board with the display daughter board 2 2 A Development Board Suite A development board suite includes the following items DK_START_GW1N LV9LQ144C6I5_V1 1 5V power adapte...

Page 12: ...wer Switch Power Socket 3 3V Power 1 2V Power 2 5V Power USB to JTAG Chip USB Interface BANK Power Selection 4 Serial FLASH 36 PIN GPIO Pin Reset Key 2 4 System Architecture Figure 2 4 System Architecture MODE LED Switch Crystal Oscillator JTAG External Clock DONE Light 40PIN GPIO Header 40PIN GPIO Header FLASH Configurat ion X36 X36 Reset X2 X4 X10 X10 X1 X1 X1 X4 X4 X4 X4 Key 20PIN LVDS Header 2...

Page 13: ...nd capacities of BSRAM Supports LV 2 FPGA Configuration Mode JTAG AUTO BOOT MSPI 3 Clock Resources 50MHz clock crystal oscillator SMA external clock input 4 Key switch and slide switch One reset button Four Key switches Four Slide switches 5 LED One power indicator green One DONE indicator green Four LEDs green 6 Memory One 64Mbit SPI flash 7 GPIO 72 I O Resources 8 LDO Power Inverse voltage prote...

Page 14: ...power to FPGA core via 3 3 V 1 2 V circuit 4 Slide Switches Available for testing 4 5 Key Switches Available for testing 4 6 Reset button Reset for FPGA 1 7 LED Test indicator DONE indicator and Power indicator Four Test indicator green One DONE indicator green One Power indicator green 8 Crystal Oscillator Provides 50MHz clock for FPGA Package5032 9 External Clock Input external clock frequency v...

Page 15: ...UG398 1 1E 8 25 No Item Functional Description Technical Condition Note connected between positive and negative anodes of power outlet 2A self recovery fuses are connected at power inlet 13 Voltage Input range 2 7V 5 5V 14 Humidity 95 15 Temperature Operating range 20 70 ...

Page 16: ... UG103 GW1N series of FPGA Products Package and Pinout 3 2 Download Interface 3 2 1 Overview The development board provides an USB download interface The data stream file can be downloaded to the internal SRAM internal flash or external flash as needed Note When downloaded to SRAM the data stream file will be lost if the device is power down and it will need to be downloaded again after power on I...

Page 17: ...e The mode is independent of the values of MODE0 and MODE1 2 Internal Flash Power on and download After downloading the data stream file successfully power down to reset and load the bit file from the internal Flash and when the Done indicator lights up to denote that the download has been successful Note Before downloading the bit file and the internal FLASH starts MODE0 and MODE1 need to set to ...

Page 18: ...SH signals configuration VCCO1 MSPI_DI_A 95 1 FLASH signals configuration VCCO1 MSPI_DO 96 1 FLASH signals configuration VCCO1 Note The VCCO1 of GW1N 9 can only be supplied with 3 3V 3 3 Power Supply 3 3 1 Overview The DC5V input power interface has overcurrent and inverse current protection The overcurrent limit is 2A The TI LDO power supply chip is used to step down voltage from 5V to 3 3V 3 3V ...

Page 19: ...CCO1 FPGA VCCO2 FPGA VCCO3 FPGA VCCX FPGA VCC FPGA LED 4 3 3 3 Power Pinout Table 3 2 GW1N 9 FPGA Power Pinout Signal Name FPGA Pins No BANK Description I O Voltage VCCO0 109 127 0 I O Bank Voltage 3 3V 2 5V 1 2V VCCO1 91 103 1 I O Bank Voltage 3 3V VCCO2 37 55 2 I O Bank Voltage 3 3V 2 5V 1 2V VCCO3 5 19 3 I O Bank Voltage 3 3V 2 5V 1 2V VCCX 31 77 Auxiliary Voltage 3 3V VCC 1 36 73 108 Core Volt...

Page 20: ...al is connected to the FPGA global clock pin 3 4 2 Clock Reset Figure 3 3 Clock Reset 6 56 92 KEY5 50MHz ADM811 JC3 660 046 3 3V FPGA_RST_N F_CLK_SMA FPGA_CLK U6 U7 J7 X2 3 4 3 Pinout Table 3 3 FPGA Clock and Reset Pinout Signal Name Pin No BANK Description I O FPGA_CLK 6 3 50MHz crystal oscillator Input 3 3V 2 5V 1 2V F_CLK_SMA 56 2 External clock input 3 3V 2 5V 1 2V FPGA_RST_N 92 1 Reset signal...

Page 21: ...ED Circuit Figure 3 4 LED Circuit D3 47 D4 57 D5 60 D6 61 VCCO2 F_LED1 F_LED2 F_LED3 F_LED4 U6 3 5 3 Pinout Table 3 4 LED Pinout Signal Name Pin No BANK Description I O F_LED1 47 2 LED1 3 3V 2 5V 1 2V F_LED2 57 2 LED2 3 3V 2 5V 1 2V F_LED3 60 2 LED3 3 3V 2 5V 1 2V F_LED4 61 2 LED4 3 3V 2 5V 1 2V 3 6 Switches 3 6 1 Overview Four slide switches are incorporated into the development board These are u...

Page 22: ...al Name Pin No BANK Description I O F_SW1 68 2 Slide Switch1 3 3V 2 5V 1 2V F_SW2 69 2 Slide Switch2 3 3V 2 5V 1 2V F_SW3 79 1 Slide Switch3 3 3V 2 5V F_SW4 80 1 Slide Switch4 3 3V 2 5V Note The VCCO1 of GW1N 9 can only be supplied with 3 3V 3 7 Key 3 7 1 Overview Four key switches are embedded in the development board Users can manually input a low level to the corresponding FPGA pins for testing...

Page 23: ... Key Pinout Signal Name Pin No BANK Description I O F_KEY1 43 2 KEY1 3 3V 2 5V 1 2V F_KEY2 44 2 KEY2 3 3V 2 5V 1 2V F_KEY3 45 2 KEY3 3 3V 2 5V 1 2V F_KEY4 46 2 KEY4 3 3V 2 5V 1 2V 3 8 GPIO 3 8 1 Overview Two 2 54mm DC3 40P sockets are reserved on the development board for user function extension and testing purposes ...

Page 24: ...10 11 13 15 17 19 12 14 16 18 20 21 23 25 27 29 22 24 26 28 30 31 33 35 37 39 32 34 36 38 40 H_B_IO1 VCC3P3 VCC5 H_B_IO3 H_B_IO5 H_B_IO7 H_B_IO9 H_B_IO11 H_B_IO13 H_B_IO15 H_B_IO17 H_B_IO19 H_B_IO21 H_B_IO23 H_B_IO25 H_B_IO27 H_B_IO29 H_B_IO31 H_B_IO33 H_B_IO35 H_B_IO2 H_B_IO4 H_B_IO6 H_B_IO8 H_B_IO10 H_B_IO12 H_B_IO14 H_B_IO16 H_B_IO18 H_B_IO20 H_B_IO22 H_B_IO24 H_B_IO26 H_B_IO28 H_B_IO30 H_B_IO3...

Page 25: ...3 H_A_IO17 9 19 3 General I O VCCO3 H_A_IO18 10 20 3 General I O VCCO3 H_A_IO19 11 21 3 General I O VCCO3 H_A_IO20 12 22 3 General I O VCCO3 H_A_IO21 15 23 3 General I O VCCO3 H_A_IO22 23 24 3 General I O VCCO3 H_A_IO23 24 25 3 General I O VCCO3 H_A_IO24 25 26 3 General I O VCCO3 H_A_IO25 26 27 3 General I O VCCO3 H_A_IO26 27 28 3 General I O VCCO3 H_A_IO27 28 29 3 General I O VCCO3 H_A_IO28 29 30...

Page 26: ...117 14 0 General I O VCCO0 H_B_IO13 116 15 0 General I O VCCO0 H_B_IO14 115 16 0 General I O VCCO0 H_B_IO15 114 17 0 General I O VCCO0 H_B_IO16 113 18 0 General I O VCCO0 H_B_IO17 112 19 0 General I O VCCO0 H_B_IO18 111 20 0 General I O VCCO0 H_B_IO19 110 21 0 General I O VCCO0 H_B_IO20 106 22 1 General I O VCCO1 H_B_IO21 104 23 1 General I O VCCO1 H_B_IO22 102 24 1 General I O VCCO1 H_B_IO23 101 ...

Page 27: ... 9 LVDS 3 9 1 Overview Two 2 mm DC3 20P sockets are reserved on the development board for LVDS testing and data communication 3 9 2 LVDS Circuit Figure 3 8 LVDS Circuit 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_A1_P F_LVDS_A2_P F_LVDS_A3_P F_LVDS_A4_P F_LVDS_A5_P F_LVDS_A1_N F_LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N F_LVDS_A5_N J10 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVD...

Page 28: ...54 10 2 Differential Channel 3 2 5V GND 11 GND 12 F_LVDS_A4_P 58 13 2 Differential Channel 4 2 5V F_LVDS_A4_N 59 14 2 Differential Channel 4 2 5V GND 15 GND 16 F_LVDS_A5_P 62 17 2 Differential Channel 5 2 5V F_LVDS_A5_N 63 18 2 Differential Channel 5 2 5V GND 19 GND 20 Table 3 10 J10 FPGA Pinout Signal Name Pin No 40P Socket Pin No BANK Description I O F_LVDS_B1_P 64 1 2 Differential Channel 1 2 5...

Page 29: ...ial Channel 3 2 5V GND 11 GND 12 F_LVDS_B4_P 72 13 2 Differential Channel 4 2 5V F_LVDS_B4_N 75 14 2 Differential Channel 4 2 5V GND 15 GND 16 F_LVDS_B5_P 76 17 2 Differential Channel 5 2 5V F_LVDS_B5_N 78 18 2 Differential Channel 5 2 5V GND 19 GND 20 Note The pin 72 and pin 75 of GW1N 9 are the none TLVDS differential output pins ...

Page 30: ...owin FPGA Products Programming and Configuration User Guide 3 100 ohm terminating resistors are welded into the LVDS Port As the output port the corresponding terminating resistors are removed in the LVDS interface 4 Input DC5V power supply via USB download interface or power socket Input via the power socket if the SW1 switch is pressed input via the USB download interface if the SW1 switch pops ...

Page 31: ...CCO of four FPGA Banks can select the voltage between 3 3V 2 5V and 1 2V through J3 to J6 pins using jumpers For GW1N 9 chip VCCO1 is 3V i e J5 jumper should be set as 3 3V VCCO0 VCCO2 and VCCO3 can be set as 3 3V 2 5V and 1 2V using jumpers ...

Page 32: ...5 Gowin Software DBUG398 1 1E 25 25 5 Gowin Software Please refer to SUG100 Gowin Software User Guide ...

Page 33: ......

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