BIOS Setup
- 106 -
Parameter
Description
NBIO RAS Common Options
Press [Enter] for more options.
NBIO RAS Global Control
– Options available: Manual/Auto. Default option is
Auto
.
NBIO RAS Control
– 0 = Disabled, 1 = MCA, 2 = Legacy.
– Options available: Disabled/MCA/Legacy. Default option is
MCA
.
Egress Poison Severity High
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
Egress Poison Severity Low
– Enter a value. Each bit set to 1 enables high severity on the
associated IOHC egress port. A bit of 0 indicates low severity.
NBIO SyncFlood Generation
– This value may be used to mask SyncFlood caused by NBIO RAS
options. When set to TRUE SyncFlood from NBIO is masked.
When set to FALSE NBIO is capable of generating SyncFlood.
– Options available: Enabled/Disabled/Auto. Default option is
Auto
.
NBIO SyncFlood Reporting
– This value may be used to enable SyncFlood reporting to APML.
When set to TRUE SyncFlood will be reported to APML. When set
to FALSE that reporting will be disabled.
– Options available: Enabled/Disabled. Default option is
Disabled
.
Egress Poison Mask High
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Egress Poison Mask Low
– Enter a value. These set the enable mask for masking of errors
logged in EGRESS_POISON_STATUS. For each bit set to 1,
errors are masked. For each bit set to 0, errors trigger response
actions.
Uncorrected Converted to Poison Enable Mask High
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Uncorrected Converted to Poison Enable Mask Low
– Enter a value. These set the enable mask for masking of
uncorrectable parity errors on internal arrays. For each bit set to
1, a system fatal error event is triggered for UCP errors on arrays
associated with that egress port. For each bit set to 0, errors are
masked.
Summary of Contents for G292-Z44
Page 1: ...G292 Z44 HPC Server 2U DP 8 x Gen4 GPU Server Broadcom solution User Manual Rev 1 0 ...
Page 10: ... 10 This page intentionally left blank ...
Page 16: ...Hardware Installation 16 This page intentionally left blank ...
Page 27: ... 27 System Hardware Installation 2 3 1 4 CPU0 CPU1 ...
Page 32: ...System Hardware Installation 32 For GPU7 GPU8 1 2 2 For GPU1 GPU2 Front Rear 1 ...
Page 33: ... 33 System Hardware Installation 1 2 2 3 4 ...
Page 35: ... 35 System Hardware Installation 1 1 2 2 For GPU3 GPU4 1 1 2 2 3 4 ...
Page 37: ... 37 System Hardware Installation 3 4 5 6 6 ...
Page 39: ... 39 System Hardware Installation 5 6 ...
Page 41: ... 41 System Hardware Installation ...
Page 48: ...System Hardware Installation 48 CPU Power MB Top Tray Connector 1 x 3 Power ...
Page 49: ... 49 System Hardware Installation HDD Backplane Board Signal HDD Backplane Board Power ...
Page 50: ...System Hardware Installation 50 Power Distribution Board to HDD Backplane Board Power SMD ...
Page 52: ...System Hardware Installation 52 Front Panel IO NVMe ...
Page 53: ... 53 System Hardware Installation NVMe Bo om Connector ...
Page 54: ...System Hardware Installation 54 NVMe Bo om Connector ...
Page 58: ...Motherboard Components 58 This page intentionally left blank ...
Page 82: ...BIOS Setup 82 5 2 13 SATA Configuration ...
Page 87: ... 87 BIOS Setup 5 2 18 Intel R I350 Gigabit Network Connection ...
Page 89: ... 89 BIOS Setup 5 2 19 VLAN Configuration ...
Page 93: ... 93 BIOS Setup 5 2 22 Intel R Ethernet Controller X550 ...